CD4072BM96

@@ -0,0 +1,74 @@+# CD4072BM96++**Texas Instruments** · Gates · SOIC-14++CD4072BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | J | output | Output of gate 1 (J = A + B + C + D). Buffered CMOS output with symmetrical source/sink drive. |+| 2 | A | input | Input A of gate 1 (4-input OR). High-impedance CMOS input, ESD-protected by internal diode/resistor network. Unused inputs must be tied to VDD or VSS. |+| 3 | B | input | Input B of gate 1 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS. |+| 4 | C | input | Input C of gate 1 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS. |+| 5 | D | input | Input D of gate 1 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS. |+| 6 | NC | unconnected | No internal connection. Leave floating or tie to any convenient rail. |+| 7 | VSS | power_in | Negative supply / ground reference. Typically 0 V; all input and output voltages are referenced to VSS. |+| 8 | NC | unconnected | No internal connection. Leave floating or tie to any convenient rail. |+| 9 | E | input | Input E of gate 2 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS. |+| 10 | F | input | Input F of gate 2 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS. |+| 11 | G | input | Input G of gate 2 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS. |+| 12 | H | input | Input H of gate 2 (4-input OR). High-impedance CMOS input; unused inputs must be tied to VDD or VSS. |+| 13 | K | output | Output of gate 2 (K = E + F + G + H). Buffered CMOS output with symmetrical source/sink drive. |+| 14 | VDD | power_in | Positive supply voltage. Operating range 3 V to 18 V; absolute maximum -0.5 V to +20 V referenced to VSS. Decouple to VSS at the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `CD4072BM96`+- `CD4072BM96E4`+- `CD4072BM96G4`+- `CD4072BM96M`+- `CD4072BM96ME4`+- `CD4072BM96MG4`+- `CD4072BM96MT`+- `CD4072BM96MTE4`+- `CD4072BM96MTG4`+- `CD4072BM96E`+- `CD4072BM96EE4`+- `CD4072BM96F`+- `CD4072BM96F3A`+- `CD4072BM96NSR`+- `CD4072BM96NSRE4`+- `CD4072BM96NSRG4`+- `CD4072BM96PW`+- `CD4072BM96PWR`+- `CD4072BM96PWE4`+- `CD4072BM96PWG4`+- `CD4072BM96PWRE4`+- `CD4072BM96PWRG4`++## CAD (KiCad official)++- Symbol: `CD4072BM96`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4072bm96.pdf) (31 pp, sha256 `81aca00a04398327`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4072bm96-datasheet.pdf)

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