component
CD4071S
Public Made by Adomby adom
GR Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD4071S
GR · Logic Gates · SOP-14
CD4071S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 2 | B | input | Input B of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 3 | J | output | OR-gate output J, which the truth table shows goes high when either of its inputs is high; the datasheet gives IOL typ 2.2 mA at VDD=5 V and IOH -1.0 mA at VDD=5 V. |
| 4 | K | output | OR-gate output K, which the truth table shows goes high when either of its inputs is high; the datasheet gives IOL typ 2.2 mA at VDD=5 V and IOH -1.0 mA at VDD=5 V. |
| 5 | C | input | Input C of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 6 | D | input | Input D of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 7 | VSS | power_in | Power ground (电源地) and the reference for the device; input and output voltages are limited relative to VSS. |
| 8 | E | input | Input E of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 9 | F | input | Input F of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 10 | L | output | OR-gate output L, which the truth table shows goes high when either of its inputs is high; the datasheet gives IOL typ 2.2 mA at VDD=5 V and IOH -1.0 mA at VDD=5 V. |
| 11 | M | output | OR-gate output M, which the truth table shows goes high when either of its inputs is high; the datasheet gives IOL typ 2.2 mA at VDD=5 V and IOH -1.0 mA at VDD=5 V. |
| 12 | G | input | Input G of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 13 | H | input | Input H of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 14 | VDD | power_in | Positive supply; the recommended operating range is 3 V to 18 V, with an absolute maximum operating voltage (VCC) of 20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum, VCC) | VCC | -0.5 | 20 | V | 1 | ||
| Input current | II | 10 | mA | 1 | |||
| Power dissipation | PD | 500 | mW | 1 | |||
| Operating temperature (absolute maximum) | TA | 0 | 70 | ℃ | 1 | ||
| Storage temperature | TS | -65 | 150 | ℃ | 1 | ||
| Lead soldering temperature | TW | 260 | ℃ | 10 s | 1 | ||
| Supply voltage (recommended operating) | VDD | 3 | 18 | V | 2 | ||
| Input/output voltage (recommended operating) | VIN, VI/O | 0 | V | upper limit printed as VDD | 2 | ||
| Operating temperature (recommended) | TA | 0 | 60 | ℃ | 2 | ||
| High-level input voltage | VIH | 3.5 | V | /IO/≤1uA, Vo=0.5V, VDD=5V | 3 | ||
| High-level input voltage | VIH | 7 | V | /IO/≤1uA, Vo=1V, VDD=10V | 3 | ||
| High-level input voltage | VIH | 11 | V | /IO/≤1uA, Vo=1.5V, VDD=15V | 3 | ||
| Low-level input voltage | VIL | 1.5 | V | /IO/≤1uA, Vo=4.5V, VDD=5V | 3 | ||
| Low-level input voltage | VIL | 3 | V | /IO/≤1uA, Vo=9V, VDD=10V | 3 | ||
| Low-level input voltage | VIL | 4 | V | /IO/≤1uA, Vo=13.5V, VDD=15V | 3 | ||
| High-level output voltage | VOH | 4.95 | V | /IOUT/<1uA, VDD=5V | 3 | ||
| High-level output voltage | VOH | 9.95 | V | /IOUT/<1uA, VDD=10V | 3 | ||
| High-level output voltage | VOH | 14.95 | V | /IOUT/<1uA, VDD=15V | 3 | ||
| Low-level output voltage | VOL | 0.05 | V | /IOUT/<1uA, VDD=5V | 3 | ||
| Input current | IIN | 0.01 | 1 | uA | VIN=VDD or VSS, VDD=18V | 3 | |
| High-level output current | IOH | -1 | mA | Vo=4.6V, VDD=5V | 3 | ||
| High-level output current | IOH | -4.3 | mA | Vo=2.5V, VDD=5V | 3 | ||
| High-level output current | IOH | -2.2 | mA | Vo=9.5V, VDD=10V | 3 | ||
| High-level output current | IOH | -8.1 | mA | Vo=13.5V, VDD=15V | 3 | ||
| Low-level output current | IOL | 2.2 | mA | Vo=0.4V, VDD=5V | 3 | ||
| Low-level output current | IOL | 5.3 | mA | Vo=0.5V, VDD=10V | 3 | ||
| Low-level output current | IOL | 20 | mA | Vo=1.5V, VDD=15V | 3 | ||
| Quiescent supply current (IDD) | IDD | 0.01 | 1 | uA | VIN=VDD or VSS, VDD=5V | 3 | |
| Quiescent supply current (IDD) | IDD | 0.01 | 2 | uA | VIN=VDD or VSS, VDD=10V | 3 | |
| Quiescent supply current (IDD) | IDD | 0.01 | 4 | uA | VIN=VDD or VSS, VDD=15V | 3 | |
| Quiescent supply current (IDD) | IDD | 0.01 | 5 | uA | VIN=VDD or VSS, VDD=18V | 3 | |
| Propagation delay INPUTS to OUTPUTS | tPHL, tPLH | 70 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=5V | 3 | ||
| Propagation delay INPUTS to OUTPUTS | tPHL, tPLH | 40 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=10V | 3 | ||
| Propagation delay INPUTS to OUTPUTS | tPHL, tPLH | 30 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=15V | 3 | ||
| Transition time | tTHL, tTLH | 35 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=5V | 3 | ||
| Transition time | tTHL, tTLH | 20 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=10V | 3 | ||
| Transition time | tTHL, tTLH | 15 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=15V | 3 |
CAD (KiCad official)
- Symbol:
CD4071S - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4071s-etched.step/cd4071s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4071s.step/cd4071s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (6 pp, sha256
17d90f09cc17a8b5, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4071S
**GR** · Logic Gates · SOP-14
CD4071S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 2 | B | input | Input B of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 3 | J | output | OR-gate output J, which the truth table shows goes high when either of its inputs is high; the datasheet gives IOL typ 2.2 mA at VDD=5 V and IOH -1.0 mA at VDD=5 V. |
| 4 | K | output | OR-gate output K, which the truth table shows goes high when either of its inputs is high; the datasheet gives IOL typ 2.2 mA at VDD=5 V and IOH -1.0 mA at VDD=5 V. |
| 5 | C | input | Input C of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 6 | D | input | Input D of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 7 | VSS | power_in | Power ground (电源地) and the reference for the device; input and output voltages are limited relative to VSS. |
| 8 | E | input | Input E of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 9 | F | input | Input F of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 10 | L | output | OR-gate output L, which the truth table shows goes high when either of its inputs is high; the datasheet gives IOL typ 2.2 mA at VDD=5 V and IOH -1.0 mA at VDD=5 V. |
| 11 | M | output | OR-gate output M, which the truth table shows goes high when either of its inputs is high; the datasheet gives IOL typ 2.2 mA at VDD=5 V and IOH -1.0 mA at VDD=5 V. |
| 12 | G | input | Input G of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 13 | H | input | Input H of the quad 2-input OR gate; per the truth table it is a logic input where 0 = low and 1 = high, with inputs limited to VSS-0.5 V to VDD+0.5 V and input current at most 1 µA (VIN=VDD=18 V, 25 °C). |
| 14 | VDD | power_in | Positive supply; the recommended operating range is 3 V to 18 V, with an absolute maximum operating voltage (VCC) of 20 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum, VCC) | VCC | -0.5 | | 20 | V | | 1 |
| Input current | II | | | 10 | mA | | 1 |
| Power dissipation | PD | | | 500 | mW | | 1 |
| Operating temperature (absolute maximum) | TA | 0 | | 70 | ℃ | | 1 |
| Storage temperature | TS | -65 | | 150 | ℃ | | 1 |
| Lead soldering temperature | TW | | | 260 | ℃ | 10 s | 1 |
| Supply voltage (recommended operating) | VDD | 3 | | 18 | V | | 2 |
| Input/output voltage (recommended operating) | VIN, VI/O | 0 | | | V | upper limit printed as VDD | 2 |
| Operating temperature (recommended) | TA | 0 | | 60 | ℃ | | 2 |
| High-level input voltage | VIH | 3.5 | | | V | /IO/≤1uA, Vo=0.5V, VDD=5V | 3 |
| High-level input voltage | VIH | 7 | | | V | /IO/≤1uA, Vo=1V, VDD=10V | 3 |
| High-level input voltage | VIH | 11 | | | V | /IO/≤1uA, Vo=1.5V, VDD=15V | 3 |
| Low-level input voltage | VIL | | | 1.5 | V | /IO/≤1uA, Vo=4.5V, VDD=5V | 3 |
| Low-level input voltage | VIL | | | 3 | V | /IO/≤1uA, Vo=9V, VDD=10V | 3 |
| Low-level input voltage | VIL | | | 4 | V | /IO/≤1uA, Vo=13.5V, VDD=15V | 3 |
| High-level output voltage | VOH | 4.95 | | | V | /IOUT/<1uA, VDD=5V | 3 |
| High-level output voltage | VOH | 9.95 | | | V | /IOUT/<1uA, VDD=10V | 3 |
| High-level output voltage | VOH | 14.95 | | | V | /IOUT/<1uA, VDD=15V | 3 |
| Low-level output voltage | VOL | | | 0.05 | V | /IOUT/<1uA, VDD=5V | 3 |
| Input current | IIN | | 0.01 | 1 | uA | VIN=VDD or VSS, VDD=18V | 3 |
| High-level output current | IOH | -1 | | | mA | Vo=4.6V, VDD=5V | 3 |
| High-level output current | IOH | -4.3 | | | mA | Vo=2.5V, VDD=5V | 3 |
| High-level output current | IOH | -2.2 | | | mA | Vo=9.5V, VDD=10V | 3 |
| High-level output current | IOH | -8.1 | | | mA | Vo=13.5V, VDD=15V | 3 |
| Low-level output current | IOL | 2.2 | | | mA | Vo=0.4V, VDD=5V | 3 |
| Low-level output current | IOL | 5.3 | | | mA | Vo=0.5V, VDD=10V | 3 |
| Low-level output current | IOL | 20 | | | mA | Vo=1.5V, VDD=15V | 3 |
| Quiescent supply current (IDD) | IDD | | 0.01 | 1 | uA | VIN=VDD or VSS, VDD=5V | 3 |
| Quiescent supply current (IDD) | IDD | | 0.01 | 2 | uA | VIN=VDD or VSS, VDD=10V | 3 |
| Quiescent supply current (IDD) | IDD | | 0.01 | 4 | uA | VIN=VDD or VSS, VDD=15V | 3 |
| Quiescent supply current (IDD) | IDD | | 0.01 | 5 | uA | VIN=VDD or VSS, VDD=18V | 3 |
| Propagation delay INPUTS to OUTPUTS | tPHL, tPLH | | | 70 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=5V | 3 |
| Propagation delay INPUTS to OUTPUTS | tPHL, tPLH | | | 40 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=10V | 3 |
| Propagation delay INPUTS to OUTPUTS | tPHL, tPLH | | | 30 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=15V | 3 |
| Transition time | tTHL, tTLH | | | 35 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=5V | 3 |
| Transition time | tTHL, tTLH | | | 20 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=10V | 3 |
| Transition time | tTHL, tTLH | | | 15 | ns | Ta=25℃, RL=200k, CL=47pF, VDD=15V | 3 |
## CAD (KiCad official)
- Symbol: `CD4071S`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4071s-etched.step` / `cd4071s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4071s.step` / `cd4071s.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [GR datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590922758979338240) (6 pp, sha256 `17d90f09cc17a8b5`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4071s-datasheet.pdf)