component
CD4071BPWR
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 2d ago |
| viewers | 2d ago |
| cd4071bpwr-etched.glb | 2d ago |
| cd4071bpwr-etched.step | 2d ago |
| cd4071bpwr-hero.glb | 1d ago |
| cd4071bpwr-hero.overlay.json | 2d ago |
| cd4071bpwr.glb | 2d ago |
| cd4071bpwr.kicad_mod | 2d ago |
| cd4071bpwr.kicad_sym | 2d ago |
| cd4071bpwr.lbr | 2d ago |
| cd4071bpwr.step | 2d ago |
| package.json | 2d ago |
| page.json | 2d ago |
| README.md | 2d ago |
CD4071BPWR
Texas Instruments · Logic Gates · TSSOP-14
CD4071BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Gate 1 input B, with output J = A OR B; input range -0.5V to VDD+0.5V. |
| 2 | A | input | Gate 1 input A, with output J = A OR B; input range -0.5V to VDD+0.5V. |
| 3 | J | output | Gate 1 OR output (A OR B) of the quad 2-input OR gate. |
| 4 | K | output | Gate 2 OR output (C OR D) of the quad 2-input OR gate. |
| 5 | D | input | Gate 2 input D, with output K = C OR D; input range -0.5V to VDD+0.5V. |
| 6 | C | input | Gate 2 input C, with output K = C OR D; input range -0.5V to VDD+0.5V. |
| 7 | VSS | power_in | Ground / negative supply; all voltages are referenced to VSS. |
| 8 | F | input | Gate 3 input F, with output L = E OR F; input range -0.5V to VDD+0.5V. |
| 9 | E | input | Gate 3 input E, with output L = E OR F; input range -0.5V to VDD+0.5V. |
| 10 | L | output | Gate 3 OR output (E OR F) of the quad 2-input OR gate. |
| 11 | M | output | Gate 4 OR output (G OR H) of the quad 2-input OR gate. |
| 12 | H | input | Gate 4 input H, with output M = G OR H; input range -0.5V to VDD+0.5V. |
| 13 | G | input | Gate 4 input G, with output M = G OR H; input range -0.5V to VDD+0.5V. |
| 14 | VDD | power_in | Positive supply; recommended 3V to 18V, absolute maximum -0.5V to +20V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4071BPWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4071bpwr-etched.step/cd4071bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4071bpwr.step/cd4071bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
e6108f3d67797b70, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).