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CD4071BP

Public Made by Adom

by adom

Sungine Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4071BP

Sungine · Gates · SOP-14

CD4071BP from Sungine, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Input 1 of OR gate A, with a protection diode clamped between VDD and VSS.
2 A2 input Input 2 of OR gate A, with a protection diode clamped between VDD and VSS.
3 YA output Output of OR gate A, with symmetric source/sink drive.
4 YB output Output of OR gate B, with symmetric source/sink drive.
5 B1 input Input 1 of OR gate B, with a protection diode clamped between VDD and VSS.
6 B2 input Input 2 of OR gate B, with a protection diode clamped between VDD and VSS.
7 VSS power_in Ground (VSS) supply pin.
8 C1 input Input 1 of OR gate C, with a protection diode clamped between VDD and VSS.
9 C2 input Input 2 of OR gate C, with a protection diode clamped between VDD and VSS.
10 YC output Output of OR gate C, with symmetric source/sink drive.
11 YD output Output of OR gate D, with symmetric source/sink drive.
12 D1 input Input 1 of OR gate D, with a protection diode clamped between VDD and VSS.
13 D2 input Input 2 of OR gate D, with a protection diode clamped between VDD and VSS.
14 VDD power_in Positive supply pin; recommended 3 to 15 V, absolute maximum -0.5 to +18 V.

Key specifications

Parameter Value
Manufacturer Sungine
Package SOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 3
Input voltage VIN -0.5 V -0.5 ~ VDD+0.5 3
Storage temperature tS -65 150 ℃ 3
Soldering temperature tL 260 ℃ 10 s 3
Operating voltage range VDD 3 15 V 3
Operating temperature range -10 70 ℃ 3
Quiescent device current IDD 0.01 1 µA VDD=5V, VIN=VDD or VSS, 25℃ 4
Quiescent device current IDD 0.01 2 µA VDD=10V, VIN=VDD or VSS, 25℃ 4
Quiescent device current IDD 0.01 4 µA VDD=15V, VIN=VDD or VSS, 25℃ 4
Low-level output voltage VOL 0 0.05 V VDD=5V, /IO/<1µA, 25℃ 4
High-level output voltage VOH 4.95 5 V VDD=5V, /IO/<1µA, 25℃ 4
High-level output voltage VOH 9.95 10 V VDD=10V, /IO/<1µA, 25℃ 4
High-level output voltage VOH 14.95 15 V VDD=15V, /IO/<1µA, 25℃ 4
Low-level input voltage VIL 2 1.5 V VDD=5V, VO=0.5V or 4.5V, 25℃ 4
Low-level input voltage VIL 4 3 V VDD=10V, VO=1.0V or 9V, 25℃ 4
Low-level input voltage VIL 6 4 V VDD=15V, VO=1.5V or 13.5V, 25℃ 4
High-level input voltage VIH 3.5 3 V VDD=5V, VO=0.5 or 4.5V, 25℃ 4
High-level input voltage VIH 7 6 V VDD=10V, VO=1.0V or 9.0V, 25℃ 4
High-level input voltage VIH 11 9 V VDD=15V, VO=1.5V or 13.5V, 25℃ 4
Low-level output current IOL 0.51 1 mA VDD=5V, VO=0.4V, 25℃ 4
Low-level output current IOL 1.3 2.8 mA VDD=10V, VO=0.5V, 25℃ 4
Low-level output current IOL 3.4 6.8 mA VDD=15V, VO=1.5V, 25℃ 4
High-level output current IOH -0.51 -1 mA VDD=5V, VO=4.6V, 25℃ 4
High-level output current IOH -1.3 -2.6 mA VDD=10V, VO=9.5V, 25℃ 4
High-level output current IOH -3.4 -6.8 mA VDD=15V, VO=13.5V, 25℃ 4
Propagation delay, high to low tPHL 100 250 ns VDD=5V, TA=25℃, RL=200KΩ, CL=50pF, tr,tf=20ns 5
Propagation delay, high to low tPHL 40 100 ns VDD=10V, TA=25℃, RL=200KΩ, CL=50pF, tr,tf=20ns 5
Propagation delay, high to low tPHL 30 70 ns VDD=15V, TA=25℃, RL=200KΩ, CL=50pF, tr,tf=20ns 5
Propagation delay, low to high tPLH 90 250 ns VDD=5V, TA=25℃, RL=200KΩ, CL=50pF, tr,tf=20ns 5
Propagation delay, low to high tPLH 40 100 ns VDD=10V, TA=25℃, RL=200KΩ, CL=50pF, tr,tf=20ns 5
Propagation delay, low to high tPLH 30 70 ns VDD=15V, TA=25℃, RL=200KΩ, CL=50pF, tr,tf=20ns 5
Transition time tTHL, tTLH 90 200 ns VDD=5V, TA=25℃, RL=200KΩ, CL=50pF, tr,tf=20ns 5
Transition time tTHL, tTLH 50 100 ns VDD=10V, TA=25℃, RL=200KΩ, CL=50pF, tr,tf=20ns 5
Transition time tTHL, tTLH 40 80 ns VDD=15V, TA=25℃, RL=200KΩ, CL=50pF, tr,tf=20ns 5
Average input capacitance CIN 5 7.5 pF Any input 5
Power dissipation capacitance CPD 18 pF Any gate 5

CAD (KiCad official)

  • Symbol: CD4071BP
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4071bp-etched.step / cd4071bp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4071bp.step / cd4071bp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Sungine datasheet (7 pp, sha256 8d28eebedbccd088, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF