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CD4071BM96

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Texas Instruments Logic Gates, SOIC-14. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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CD4071BM96

Texas Instruments · Logic Gates · SOIC-14

CD4071BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of OR gate 1 (2-input OR); input voltage range is -0.5V to VDD+0.5V and DC input current is limited to ±10mA, per CMOS protection network.
2 1B input Input B of OR gate 1 (2-input OR); input voltage range is -0.5V to VDD+0.5V and DC input current is limited to ±10mA, per CMOS protection network.
3 1Y output Output of OR gate 1, Y = A OR B; power dissipation per output transistor is limited to 100mW over the full package temperature range.
4 2Y output Output of OR gate 2, Y = A OR B; power dissipation per output transistor is limited to 100mW over the full package temperature range.
5 2B input Input B of OR gate 2 (2-input OR); input voltage range is -0.5V to VDD+0.5V and DC input current is limited to ±10mA, per CMOS protection network.
6 2A input Input A of OR gate 2 (2-input OR); input voltage range is -0.5V to VDD+0.5V and DC input current is limited to ±10mA, per CMOS protection network.
7 VSS power_in Negative supply/ground reference pin; DC supply-voltage range VDD is specified as -0.5V to +20V referenced to this VSS terminal.
8 3A input Input A of OR gate 3 (2-input OR); input voltage range is -0.5V to VDD+0.5V and DC input current is limited to ±10mA, per CMOS protection network.
9 3B input Input B of OR gate 3 (2-input OR); input voltage range is -0.5V to VDD+0.5V and DC input current is limited to ±10mA, per CMOS protection network.
10 3Y output Output of OR gate 3, Y = A OR B; power dissipation per output transistor is limited to 100mW over the full package temperature range.
11 4Y output Output of OR gate 4, Y = A OR B; power dissipation per output transistor is limited to 100mW over the full package temperature range.
12 4B input Input B of OR gate 4 (2-input OR); input voltage range is -0.5V to VDD+0.5V and DC input current is limited to ±10mA, per CMOS protection network.
13 4A input Input A of OR gate 4 (2-input OR); input voltage range is -0.5V to VDD+0.5V and DC input current is limited to ±10mA, per CMOS protection network.
14 VDD power_in Positive supply pin; DC supply-voltage range is -0.5V to +20V referenced to the VSS terminal.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4071BM96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4071bm96-etched.step / cd4071bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4071bm96.step / cd4071bm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 e6108f3d67797b70, retrieved 2026-09-29, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF