component
CD4070S
Public Made by Adomby adom
GR Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+55@@ -0,0 +1,55 @@+# CD4070S++**GR** · Gates · SOP-14++CD4070S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Input A of gate 1 (J = A XOR B). CMOS logic input, VIH >= 3.5 V @ VDD=5 V; input leakage <= 1 uA. |+| 2 | B | input | Input B of gate 1 (J = A XOR B). CMOS logic input. |+| 3 | J | output | Output J of gate 1 (J = A XOR B). CMOS push-pull output; VOH ~ VDD-0.05 V, VOL ~ 0.05 V at |IOUT| < 1 uA. |+| 4 | K | output | Output K of gate 2 (K = C XOR D). CMOS push-pull output. |+| 5 | C | input | Input C of gate 2 (K = C XOR D). CMOS logic input. |+| 6 | D | input | Input D of gate 2 (K = C XOR D). CMOS logic input. |+| 7 | VSS | power_in | Ground / negative supply rail (0 V reference). Absolute max VCC (VDD-VSS) = 18 V. |+| 8 | E | input | Input E of gate 3 (L = E XOR F). CMOS logic input. |+| 9 | F | input | Input F of gate 3 (L = E XOR F). CMOS logic input. |+| 10 | L | output | Output L of gate 3 (L = E XOR F). CMOS push-pull output. |+| 11 | M | output | Output M of gate 4 (M = G XOR H). CMOS push-pull output. |+| 12 | G | input | Input G of gate 4 (M = G XOR H). CMOS logic input. |+| 13 | H | input | Input H of gate 4 (M = G XOR H). CMOS logic input. |+| 14 | VDD | power_in | Positive supply rail. Recommended operating range 3.0 V to 15.0 V; absolute max 18 V referenced to VSS. Typical quiescent current 0.01 uA @ VDD=15 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GR |+| Package | SOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `CD4070SS`+- `CD4070SD`++## CAD (KiCad official)++- Symbol: `CD4070S`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GR datasheet](docs/cd4070s-datasheet.pdf) (6 pp, sha256 `23e82fbab3d6a9d7`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4070s-datasheet.pdf)
page.jsonadded+34@@ -0,0 +1,34 @@+{+ "slug": "cd4070s",+ "version": "0.1.0",+ "type": "component",+ "description": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4070s"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4070s.kicad_sym",+ "cd4070s.kicad_mod",+ "cd4070s.glb",+ "cd4070s.step",+ "cd4070s.lbr",+ "docs/hero.png",+ "docs/cd4070s-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "visibility": "public",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}