component
CD4070S
Public Made by Adomby adom
GR Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+152−8@@ -1,13 +1,162 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4070s",+ "title": "CD4070S",+ "brief": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "GR Gates, SOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "cd4070s" ],+ "component": {+ "mpn": "CD4070S",+ "manufacturer": "GR",+ "package": "SOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Gates",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403121628_GR-CD4070S_C22357617.pdf",+ "parts": {+ "symbol": "cd4070s.kicad_sym",+ "footprint": "cd4070s.kicad_mod",+ "model_3d": "cd4070s.glb",+ "model_3d_step": "cd4070s.step",+ "lbr": "cd4070s.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Input A of gate 1 (J = A XOR B). CMOS logic input, VIH >= 3.5 V @ VDD=5 V; input leakage <= 1 uA."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Input B of gate 1 (J = A XOR B). CMOS logic input."+ },+ {+ "number": "3",+ "name": "J",+ "type": "output",+ "description": "Output J of gate 1 (J = A XOR B). CMOS push-pull output; VOH ~ VDD-0.05 V, VOL ~ 0.05 V at |IOUT| < 1 uA."+ },+ {+ "number": "4",+ "name": "K",+ "type": "output",+ "description": "Output K of gate 2 (K = C XOR D). CMOS push-pull output."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Input C of gate 2 (K = C XOR D). CMOS logic input."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Input D of gate 2 (K = C XOR D). CMOS logic input."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground / negative supply rail (0 V reference). Absolute max VCC (VDD-VSS) = 18 V."+ },+ {+ "number": "8",+ "name": "E",+ "type": "input",+ "description": "Input E of gate 3 (L = E XOR F). CMOS logic input."+ },+ {+ "number": "9",+ "name": "F",+ "type": "input",+ "description": "Input F of gate 3 (L = E XOR F). CMOS logic input."+ },+ {+ "number": "10",+ "name": "L",+ "type": "output",+ "description": "Output L of gate 3 (L = E XOR F). CMOS push-pull output."+ },+ {+ "number": "11",+ "name": "M",+ "type": "output",+ "description": "Output M of gate 4 (M = G XOR H). CMOS push-pull output."+ },+ {+ "number": "12",+ "name": "G",+ "type": "input",+ "description": "Input G of gate 4 (M = G XOR H). CMOS logic input."+ },+ {+ "number": "13",+ "name": "H",+ "type": "input",+ "description": "Input H of gate 4 (M = G XOR H). CMOS logic input."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply rail. Recommended operating range 3.0 V to 15.0 V; absolute max 18 V referenced to VSS. Typical quiescent current 0.01 uA @ VDD=15 V."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403121628_GR-CD4070S_C22357617.pdf",+ "pages": 6,+ "sha256": "23e82fbab3d6a9d7",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "GR",+ "Package": "SOP-14",+ "Category": "Logic",+ "Pins": "14"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "cd4070s"+ ],+ "discovery_pitch": "CD4070S (GR) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +174,5 @@ "docs/cd4070s-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }