component
CD4070CMT
Public Made by Adomby adom
HGSEMI Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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cd4070cmt: laser-etched CAD + chip hero (factory 2.0.0 backfill)
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CD4070CMT
HGSEMI · Gates · TSSOP-14
CD4070CMT from HGSEMI, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of XOR gate 1 (J = A XOR B). CMOS logic input, VIH >= 0.7VDD, VIL <= 0.3VDD, IIN <= 1 uA @ VDD = 15 V. |
| 2 | B | input | Input B of XOR gate 1 (J = A XOR B). CMOS logic input. |
| 3 | J | output | Output J of XOR gate 1 (J = A XOR B). CMOS push-pull output; IOH ~= -14 mA and IOL ~= 28 mA typical at VDD = 15 V. |
| 4 | K | output | Output K of XOR gate 2 (K = C XOR D). CMOS push-pull output. |
| 5 | C | input | Input C of XOR gate 2 (K = C XOR D). CMOS logic input. |
| 6 | D | input | Input D of XOR gate 2 (K = C XOR D). CMOS logic input. |
| 7 | VSS | power_in | Negative supply / ground reference (0 V). All logic levels referenced to VSS. |
| 8 | E | input | Input E of XOR gate 3 (L = E XOR F). CMOS logic input. |
| 9 | F | input | Input F of XOR gate 3 (L = E XOR F). CMOS logic input. |
| 10 | L | output | Output L of XOR gate 3 (L = E XOR F). CMOS push-pull output. |
| 11 | M | output | Output M of XOR gate 4 (M = G XOR H). CMOS push-pull output. |
| 12 | G | input | Input G of XOR gate 4 (M = G XOR H). CMOS logic input. |
| 13 | H | input | Input H of XOR gate 4 (M = G XOR H). CMOS logic input. |
| 14 | VDD | power_in | Positive supply, 3.0 V to 15.0 V (absolute max 18 V). Bypass with a local ceramic capacitor to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
CD4070CMT/TRCD4070CMTCM/TRCD4070CMTCN
CAD (KiCad official)
- Symbol:
CD4070CMT - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4070cmt-etched.step/cd4070cmt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4070cmt.step/cd4070cmt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (9 pp, sha256
1ce55545a5113aef, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4070CMT
**HGSEMI** · Gates · TSSOP-14
CD4070CMT from HGSEMI, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of XOR gate 1 (J = A XOR B). CMOS logic input, VIH >= 0.7*VDD, VIL <= 0.3*VDD, IIN <= 1 uA @ VDD = 15 V. |
| 2 | B | input | Input B of XOR gate 1 (J = A XOR B). CMOS logic input. |
| 3 | J | output | Output J of XOR gate 1 (J = A XOR B). CMOS push-pull output; IOH ~= -14 mA and IOL ~= 28 mA typical at VDD = 15 V. |
| 4 | K | output | Output K of XOR gate 2 (K = C XOR D). CMOS push-pull output. |
| 5 | C | input | Input C of XOR gate 2 (K = C XOR D). CMOS logic input. |
| 6 | D | input | Input D of XOR gate 2 (K = C XOR D). CMOS logic input. |
| 7 | VSS | power_in | Negative supply / ground reference (0 V). All logic levels referenced to VSS. |
| 8 | E | input | Input E of XOR gate 3 (L = E XOR F). CMOS logic input. |
| 9 | F | input | Input F of XOR gate 3 (L = E XOR F). CMOS logic input. |
| 10 | L | output | Output L of XOR gate 3 (L = E XOR F). CMOS push-pull output. |
| 11 | M | output | Output M of XOR gate 4 (M = G XOR H). CMOS push-pull output. |
| 12 | G | input | Input G of XOR gate 4 (M = G XOR H). CMOS logic input. |
| 13 | H | input | Input H of XOR gate 4 (M = G XOR H). CMOS logic input. |
| 14 | VDD | power_in | Positive supply, 3.0 V to 15.0 V (absolute max 18 V). Bypass with a local ceramic capacitor to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Ordering variants
Same part, different packaging or reel option.
- `CD4070CMT/TR`
- `CD4070CMTCM/TR`
- `CD4070CMTCN`
## CAD (KiCad official)
- Symbol: `CD4070CMT`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4070cmt-etched.step` / `cd4070cmt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4070cmt.step` / `cd4070cmt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [HGSEMI datasheet](docs/cd4070cmt-datasheet.pdf) (9 pp, sha256 `1ce55545a5113aef`, retrieved 2026-08-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4070cmt-datasheet.pdf)