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CD4070CM

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HGSEMI Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4070CM

HGSEMI · Logic Gates · SOP-14

CD4070CM from HGSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Logic input A of the exclusive-OR network; its voltage must stay between VSS and VDD (recommended range 0 to VDD).
2 B input Logic input B of the exclusive-OR network; its voltage must stay between VSS and VDD (recommended range 0 to VDD).
3 J output XOR gate output J, which is high when its paired inputs differ, per the truth table.
4 K output XOR gate output K, which is high when its paired inputs differ, per the truth table.
5 C input Logic input C of the exclusive-OR network; its voltage must stay between VSS and VDD (recommended range 0 to VDD).
6 D input Logic input D of the exclusive-OR network; its voltage must stay between VSS and VDD (recommended range 0 to VDD).
7 VSS power_in Power supply ground (negative supply) for the device.
8 E input Logic input E of the exclusive-OR network; its voltage must stay between VSS and VDD (recommended range 0 to VDD).
9 F input Logic input F of the exclusive-OR network; its voltage must stay between VSS and VDD (recommended range 0 to VDD).
10 L output XOR gate output L, which is high when its paired inputs differ, per the truth table.
11 M output XOR gate output M, which is high when its paired inputs differ, per the truth table.
12 G input Logic input G of the exclusive-OR network; its voltage must stay between VSS and VDD (recommended range 0 to VDD).
13 H input Logic input H of the exclusive-OR network; its voltage must stay between VSS and VDD (recommended range 0 to VDD).
14 VDD power_in Positive power supply; the datasheet specifies an operating range of 3 V to 15 V.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 18 V 3
Input/output voltage VIN, VI/O -0.5 V Printed as -0.5 to VSS-VDD+0.5 V; upper limit is not numeric 3
Input current II 10 mA 3
Power dissipation PD 500 mW 3
Operating temperature TA 0 70 ℃ 3
Storage temperature TS -65 150 ℃ 3
Lead soldering temperature TW 245 ℃ 10 s 3
Supply voltage VDD 3 15 V 4
Input/output voltage VIN, VI/O 0 V Maximum printed as VDD 4
Operating temperature TA 0 60 ℃ 4
High-level input voltage VIH 3.5 V Ta=25℃; /IO/≤1uA; Vo=0.5V; VDD=5V 4
High-level input voltage VIH 7 V Ta=25℃; /IO/≤1uA; Vo=1V; VDD=10V 4
High-level input voltage VIH 11 V Ta=25℃; /IO/≤1uA; Vo=1.5V; VDD=15V 4
Low-level input voltage VIL 1.5 V Ta=25℃; /IO/≤1uA; Vo=4.5V; VDD=5V 4
Low-level input voltage VIL 3 V Ta=25℃; /IO/≤1uA; Vo=9V; VDD=10V 4
Low-level input voltage VIL 4 V Ta=25℃; /IO/≤1uA; Vo=13.5V; VDD=15V 4
High-level output voltage VOH 4.95 V Ta=25℃; /IOUT/<1uA; VDD=5V 4
High-level output voltage VOH 9.95 V Ta=25℃; /IOUT/<1uA; VDD=10V 4
High-level output voltage VOH 14.95 V Ta=25℃; /IOUT/<1uA; VDD=15V 4
Low-level output voltage VOL 0.05 V Ta=25℃; /IOUT/<1uA; VDD=5V 4
Input current IIN 0.01 1 uA Ta=25℃; VIN=VDD or VSS; VDD=15V 4
High-level output current IOH -1.8 mA Ta=25℃; Vo=4.6V; VDD=5V 4
High-level output current IOH -3.8 mA Ta=25℃; Vo=9.5V; VDD=10V 4
High-level output current IOH -14 mA Ta=25℃; Vo=13.5V; VDD=15V 4
Low-level output current IOL 3 mA Ta=25℃; Vo=0.4V; VDD=5V 4
Low-level output current IOL 7.5 mA Ta=25℃; Vo=0.5V; VDD=10V 4
Low-level output current IOL 28 mA Ta=25℃; Vo=1.5V; VDD=15V 4
Operating current IDD 0.01 1 uA Ta=25℃; VIN=VDD or VSS; VDD=5V 4
Operating current IDD 0.01 2 uA Ta=25℃; VIN=VDD or VSS; VDD=10V 4
Operating current IDD 0.01 5 uA Ta=25℃; VIN=VDD or VSS; VDD=15V 4
Propagation delay, INPUTS to OUTPUTS tPHL tPLH 70 ns Ta=25℃, RL=200k, CL=47pF; VDD=5V 5
Propagation delay, INPUTS to OUTPUTS tPHL tPLH 50 ns Ta=25℃, RL=200k, CL=47pF; VDD=10V 5
Propagation delay, INPUTS to OUTPUTS tPHL tPLH 30 ns Ta=25℃, RL=200k, CL=47pF; VDD=15V 5
Transition time tTHL tTLH 30 ns Ta=25℃, RL=200k, CL=47pF; VDD=5V 5
Transition time tTHL tTLH 25 ns Ta=25℃, RL=200k, CL=47pF; VDD=10V 5
Transition time tTHL tTLH 20 ns Ta=25℃, RL=200k, CL=47pF; VDD=15V 5

CAD (KiCad official)

  • Symbol: CD4070CM
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4070cm-etched.step / cd4070cm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4070cm.step / cd4070cm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (9 pp, sha256 1ce55545a5113aef, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF