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CD4070BPWR

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Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4070BPWR

Texas Instruments · Logic Gates · TSSOP-14

CD4070BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Input A of the first exclusive-OR gate (J = A ⊕ B); inputs are protected by a CMOS protection network and input voltage is limited to -0.5 V to VDD + 0.5 V.
2 B input Input B of the first exclusive-OR gate (J = A ⊕ B); inputs are protected by a CMOS protection network and input voltage is limited to -0.5 V to VDD + 0.5 V.
3 J output Output of the first exclusive-OR gate, J = A ⊕ B, with symmetrical output characteristics.
4 K output Output of the second exclusive-OR gate, K = C ⊕ D, with symmetrical output characteristics.
5 C input Input C of the second exclusive-OR gate (K = C ⊕ D); inputs are protected by a CMOS protection network and input voltage is limited to -0.5 V to VDD + 0.5 V.
6 D input Input D of the second exclusive-OR gate (K = C ⊕ D); inputs are protected by a CMOS protection network and input voltage is limited to -0.5 V to VDD + 0.5 V.
7 VSS power_in Negative supply / ground reference terminal of the device; the DC supply range is specified relative to VSS with VDD from -0.5 V to 20 V absolute maximum and 3 V to 18 V typical.
8 E input Input E of the third exclusive-OR gate (L = E ⊕ F); inputs are protected by a CMOS protection network and input voltage is limited to -0.5 V to VDD + 0.5 V.
9 F input Input F of the third exclusive-OR gate (L = E ⊕ F); inputs are protected by a CMOS protection network and input voltage is limited to -0.5 V to VDD + 0.5 V.
10 L output Output of the third exclusive-OR gate, L = E ⊕ F, with symmetrical output characteristics.
11 M output Output of the fourth exclusive-OR gate, M = G ⊕ H, with symmetrical output characteristics.
12 G input Input G of the fourth exclusive-OR gate (M = G ⊕ H); inputs are protected by a CMOS protection network and input voltage is limited to -0.5 V to VDD + 0.5 V.
13 H input Input H of the fourth exclusive-OR gate (M = G ⊕ H); inputs are protected by a CMOS protection network and input voltage is limited to -0.5 V to VDD + 0.5 V.
14 VDD power_in Positive supply terminal; DC supply voltage range is -0.5 V to 20 V absolute maximum, with 3 V to 18 V typical operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Quiescent Device Current IDD 0.01 0.25 µA VIN=0,5 V; VDD=5 V; TA=25°C 4
Quiescent Device Current IDD 0.01 0.5 µA VIN=0,10 V; VDD=10 V; TA=25°C 4
Quiescent Device Current IDD 0.01 1 µA VIN=0,15 V; VDD=15 V; TA=25°C 4
Quiescent Device Current IDD 0.02 5 µA VIN=0,20 V; VDD=20 V; TA=25°C 4
Quiescent Device Current IDD 7.5 µA VIN=0,5 V; VDD=5 V; TA=125°C 4
Quiescent Device Current IDD 15 µA VIN=0,10 V; VDD=10 V; TA=125°C 4
Quiescent Device Current IDD 30 µA VIN=0,15 V; VDD=15 V; TA=125°C 4
Quiescent Device Current IDD 150 µA VIN=0,20 V; VDD=20 V; TA=125°C 4
Output Low (Sink) Current IOL 0.51 1 mA VO=0.4 V; VIN=0,5 V; VDD=5 V; TA=25°C 4
Output Low (Sink) Current IOL 1.3 2.6 mA VO=0.5 V; VIN=0,10 V; VDD=10 V; TA=25°C 4
Output Low (Sink) Current IOL 3.4 6.8 mA VO=1.5 V; VIN=0,15 V; VDD=15 V; TA=25°C 4
Output Low (Sink) Current IOL 0.36 mA VO=0.4 V; VIN=0,5 V; VDD=5 V; TA=125°C 4
Output Low (Sink) Current IOL 0.9 mA VO=0.5 V; VIN=0,10 V; VDD=10 V; TA=125°C 4
Output Low (Sink) Current IOL 2.4 mA VO=1.5 V; VIN=0,15 V; VDD=15 V; TA=125°C 4
Output High (Source) Current IOH -0.51 -1 mA VO=4.6 V; VIN=0,5 V; VDD=5 V; TA=25°C 4
Output High (Source) Current IOH -1.6 -3.2 mA VO=2.5 V; VIN=0,5 V; VDD=5 V; TA=25°C 4
Output High (Source) Current IOH -1.3 -2.6 mA VO=9.5 V; VIN=0,10 V; VDD=10 V; TA=25°C 4
Output High (Source) Current IOH -3.4 -6.8 mA VO=13.5 V; VIN=0,15 V; VDD=15 V; TA=25°C 4
Output High (Source) Current IOH -0.36 mA VO=4.6 V; VIN=0,5 V; VDD=5 V; TA=125°C 4
Output High (Source) Current IOH -1.15 mA VO=2.5 V; VIN=0,5 V; VDD=5 V; TA=125°C 4
Output High (Source) Current IOH -0.9 mA VO=9.5 V; VIN=0,10 V; VDD=10 V; TA=125°C 4
Output High (Source) Current IOH -2.4 mA VO=13.5 V; VIN=0,15 V; VDD=15 V; TA=125°C 4
Output Voltage: Low Level VOL 0 0.05 V VIN=0,5 V; VDD=5 V; TA=25°C 4
Output Voltage: High Level VOH 4.95 5 V VIN=0,5 V; VDD=5 V; TA=25°C 4
Output Voltage: High Level VOH 9.95 10 V VIN=0,10 V; VDD=10 V; TA=25°C 4
Output Voltage: High Level VOH 14.95 15 V VIN=0,15 V; VDD=15 V; TA=25°C 4
Input Low Voltage VIL 1.5 V VO=0.5,4.5 V; VDD=5 V; TA=25°C 4
Input Low Voltage VIL 3 V VO=1,9 V; VDD=10 V; TA=25°C 4
Input Low Voltage VIL 4 V VO=1.5,13.5 V; VDD=15 V; TA=25°C 4
Input High Voltage VIH 3.5 V VO=0.5,4.5 V; VDD=5 V; TA=25°C 4
Input High Voltage VIH 7 V VO=1,9 V; VDD=10 V; TA=25°C 4
Input High Voltage VIH 11 V VO=1.5,13.5 V; VDD=15 V; TA=25°C 4
Input Current IIN -0.1 0.1 µA VIN=0,18 V; VDD=18 V; TA=25°C 4
Input Current IIN -1 1 µA VIN=0,18 V; VDD=18 V; TA=125°C 4
Propagation Delay Time tPHL, tPLH 140 280 ns VDD=5 V; TA=25°C; tr=tf=20 ns; CL=50 pF; RL=200 kΩ 5
Propagation Delay Time tPHL, tPLH 65 130 ns VDD=10 V; TA=25°C; tr=tf=20 ns; CL=50 pF; RL=200 kΩ 5
Propagation Delay Time tPHL, tPLH 50 100 ns VDD=15 V; TA=25°C; tr=tf=20 ns; CL=50 pF; RL=200 kΩ 5
Transition Time tTHL, tTLH 100 200 ns VDD=5 V; TA=25°C; tr=tf=20 ns; CL=50 pF; RL=200 kΩ 5
Transition Time tTHL, tTLH 50 100 ns VDD=10 V; TA=25°C; tr=tf=20 ns; CL=50 pF; RL=200 kΩ 5
Transition Time tTHL, tTLH 40 80 ns VDD=15 V; TA=25°C; tr=tf=20 ns; CL=50 pF; RL=200 kΩ 5
DC Supply Voltage Range VDD -0.5 20 V 4
Input Voltage Range, All Inputs VIN -0.5 V 4
DC Input Current -10 10 mA 4
Maximum Storage Temperature Range -65 150 °C 4
Maximum Junction Temperature (Plastic Package) 150 °C 4
Temperature Range TA -55 125 °C 4
Supply Voltage Range (Typical) 3 18 V 4
Package Thermal Impedance, PW (TSSOP) Package θJA 113 °C/W PW (TSSOP) package, per JESD 51-7 (Note 1) 4

CAD (KiCad official)

  • Symbol: CD4070BPWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4070bpwr-etched.step / cd4070bpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4070bpwr.step / cd4070bpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 2c6477df1a6cc4c1, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF