component
CD4070BP
Public Made by Adomby adom
Sungine Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownCD4070BP
Sungine · Logic Gates · SOP-14
CD4070BP from Sungine, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of gate J (J = A XOR B); inputs are clamped by protection diodes between VDD and VSS, with recommended input voltage 0 to VDD. |
| 2 | B | input | Input B of gate J (J = A XOR B); inputs are clamped by protection diodes between VDD and VSS, with recommended input voltage 0 to VDD. |
| 3 | J | output | Output of gate J = A XOR B, with symmetric source/sink drive capability. |
| 4 | K | output | Output of gate K = C XOR D, with symmetric source/sink drive capability. |
| 5 | C | input | Input C of gate K (K = C XOR D); inputs are clamped by protection diodes between VDD and VSS, with recommended input voltage 0 to VDD. |
| 6 | D | input | Input D of gate K (K = C XOR D); inputs are clamped by protection diodes between VDD and VSS, with recommended input voltage 0 to VDD. |
| 7 | VSS | power_in | Ground supply pin (VSS = 0 V). |
| 8 | E | input | Input E of gate L (L = E XOR F); inputs are clamped by protection diodes between VDD and VSS, with recommended input voltage 0 to VDD. |
| 9 | F | input | Input F of gate L (L = E XOR F); inputs are clamped by protection diodes between VDD and VSS, with recommended input voltage 0 to VDD. |
| 10 | L | output | Output of gate L = E XOR F, with symmetric source/sink drive capability. |
| 11 | M | output | Output of gate M = G XOR H, with symmetric source/sink drive capability. |
| 12 | G | input | Input G of gate M (M = G XOR H); inputs are clamped by protection diodes between VDD and VSS, with recommended input voltage 0 to VDD. |
| 13 | H | input | Input H of gate M (M = G XOR H); inputs are clamped by protection diodes between VDD and VSS, with recommended input voltage 0 to VDD. |
| 14 | VDD | power_in | Positive supply pin; recommended 3 to 15 V, absolute maximum -0.5 to +18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Sungine |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | -0.5 | 18 | V | 2 | ||
| Input voltage | VIN | -0.5 | V | -0.5 ~ VDD+0.5 | 2 | ||
| Storage temperature | tS | -65 | 150 | °C | 2 | ||
| Power dissipation SOP | PD | 500 | mW | SOP | 3 | ||
| Soldering temperature | tL | 260 | °C | 10 s | 3 | ||
| Supply voltage | VDD | 3 | 15 | V | 3 | ||
| Input voltage | VIN | 0 | V | 0 ~ VDD | 3 | ||
| Operating temperature | tA | -10 | 70 | °C | 3 | ||
| Quiescent current | IDD | 1 | µA | VDD=5V, VIN=VDD or VSS, 25°C | 3 | ||
| Quiescent current | IDD | 2 | µA | VDD=10V, VIN=VDD or VSS, 25°C | 3 | ||
| Quiescent current | IDD | 4 | µA | VDD=15V, VIN=VDD or VSS, 25°C | 3 | ||
| Low-level output voltage | VOL | 0 | 0.05 | V | VDD=5V, /IO/<1µA, 25°C | 3 | |
| High-level output voltage | VOH | 4.95 | 5 | V | VDD=5V, /IO/<1µA, 25°C | 4 | |
| High-level output voltage | VOH | 9.95 | 10 | V | VDD=10V, /IO/<1µA, 25°C | 4 | |
| High-level output voltage | VOH | 14.95 | 15 | V | VDD=15V, /IO/<1µA, 25°C | 4 | |
| Low-level input voltage | VIL | 1.5 | V | VDD=5V, VO=0.5V or 4.5V | 4 | ||
| Low-level input voltage | VIL | 3 | V | VDD=10V, VO=1.0V or 9V | 4 | ||
| Low-level input voltage | VIL | 4 | V | VDD=15V, VO=1.5V or 13.5V | 4 | ||
| High-level input voltage | VIH | 3.5 | V | VDD=5V, VO=0.5 or 4.5V | 4 | ||
| High-level input voltage | VIH | 7 | V | VDD=10V, VO=1.0V or 9.0V | 4 | ||
| High-level input voltage | VIH | 11 | V | VDD=15V, VO=1.5V or 13.5V | 4 | ||
| Low-level output current | IOL | 0.51 | 1 | mA | VDD=5V, VO=0.4V, 25°C | 4 | |
| Low-level output current | IOL | 1.3 | 2.8 | mA | VDD=10V, VO=0.5V, 25°C | 4 | |
| Low-level output current | IOL | 3.4 | 6.8 | mA | VDD=15V, VO=1.5V, 25°C | 4 | |
| High-level output current | IOH | -0.51 | -1 | mA | VDD=5V, VO=4.6V, 25°C | 4 | |
| High-level output current | IOH | -1.3 | -2.6 | mA | VDD=10V, VO=9.5V, 25°C | 4 | |
| High-level output current | IOH | -3.4 | -6.8 | mA | VDD=15V, VO=13.5V, 25°C | 4 | |
| Propagation delay input to output | tPHL, tPLH | 110 | 185 | ns | VDD=5V, TA=25°C, RL=200kΩ, CL=50pF, tr,tf=20ns | 5 | |
| Propagation delay input to output | tPHL, tPLH | 50 | 90 | ns | VDD=10V, TA=25°C, RL=200kΩ, CL=50pF, tr,tf=20ns | 5 | |
| Propagation delay input to output | tPHL, tPLH | 40 | 75 | ns | VDD=15V, TA=25°C, RL=200kΩ, CL=50pF, tr,tf=20ns | 5 | |
| Transition time | tTHL, tTLH | 100 | 200 | ns | VDD=5V, TA=25°C, RL=200kΩ, CL=50pF, tr,tf=20ns | 5 | |
| Transition time | tTHL, tTLH | 50 | 100 | ns | VDD=10V, TA=25°C, RL=200kΩ, CL=50pF, tr,tf=20ns | 5 | |
| Transition time | tTHL, tTLH | 40 | 80 | ns | VDD=15V, TA=25°C, RL=200kΩ, CL=50pF, tr,tf=20ns | 5 | |
| Average input capacitance | CIN | 5 | 7.5 | pF | any input | 5 | |
| Power dissipation capacitance | CPD | 20 | pF | any input | 5 |
CAD (KiCad official)
- Symbol:
CD4070BP - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4070bp-etched.step/cd4070bp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4070bp.step/cd4070bp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Sungine datasheet (7 pp, sha256
b64c4b31341fac5e, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).