component
CD4070BM
Public Made by Adomby adom
lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "CD4070BM",
"brief": "lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
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"package": "SOP-14",
"pin_count": 14,
"category": "Logic",
"subcategory": "Logic Gates",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388815683690496",
"parts": {
"symbol": "cd4070bm.kicad_sym",
"footprint": "cd4070bm.kicad_mod",
"model_3d": "cd4070bm-hero.glb",
"model_3d_plain": "cd4070bm-etched.glb",
"model_3d_step": "cd4070bm-etched.step",
"model_3d_step_plain": "cd4070bm.step",
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"distributor_links": {
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{
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"name": "1A",
"type": "input",
"description": "Data input for gate 1; unused inputs must be connected to VDD, VSS, or another input."
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{
"number": "2",
"name": "1B",
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"description": "Data input for gate 1; unused inputs must be connected to VDD, VSS, or another input."
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{
"number": "3",
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"description": "Fully buffered data output of gate 1 (Y = A XOR B)."
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{
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"description": "Fully buffered data output of gate 2 (Y = A XOR B)."
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{
"number": "5",
"name": "2A",
"type": "input",
"description": "Data input for gate 2; unused inputs must be connected to VDD, VSS, or another input."
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{
"number": "6",
"name": "2B",
"type": "input",
"description": "Data input for gate 2; unused inputs must be connected to VDD, VSS, or another input."
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{
"number": "7",
"name": "VSS",
"type": "power_in",
"description": "Ground (0 V) reference for the device; all voltages are referenced to VSS."
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{
"number": "8",
"name": "3A",
"type": "input",
"description": "Data input for gate 3; unused inputs must be connected to VDD, VSS, or another input."
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{
"number": "9",
"name": "3B",
"type": "input",
"description": "Data input for gate 3; unused inputs must be connected to VDD, VSS, or another input."
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{
"number": "10",
"name": "3Y",
"type": "output",
"description": "Fully buffered data output of gate 3 (Y = A XOR B)."
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{
"number": "11",
"name": "4Y",
"type": "output",
"description": "Fully buffered data output of gate 4 (Y = A XOR B)."
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{
"number": "12",
"name": "4A",
"type": "input",
"description": "Data input for gate 4; unused inputs must be connected to VDD, VSS, or another input."
},
{
"number": "13",
"name": "4B",
"type": "input",
"description": "Data input for gate 4; unused inputs must be connected to VDD, VSS, or another input."
},
{
"number": "14",
"name": "VDD",
"type": "power_in",
"description": "Supply voltage; recommended range 3 V to 15 V referenced to VSS, absolute maximum 18 V."
}
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"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
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"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The pin configuration diagram on page 4 is an image with no text, so the pin mapping is taken from t; The ordering tables list CD4070BM alongside CD4070BE and CD4070PW, but do not explicitly map CD4070B; Output type for pins 3, 4, 10 and 11 is set to 'output' and pins 1, 2, 5, 6, 8, 9, 12 and 13 to 'inp"
],
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"cost_usd": 0.0436,
"at": "2026-10-17T17:21:14"
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"sha256": "456878778715ecb0",
"source_tier": "lcsc"
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"cad": "KiCad official (CC-BY-SA 4.0)",
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"described": 14,
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"refuses_to_fabricate": true
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"Package": "SOP-14",
"Category": "Logic",
"Pins": "14"
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"name": "LOW-level output current",
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{
"name": "HIGH-level output current",
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"conditions": "VIN 0,15; VDD 15V; Tamb=25℃",
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"conditions": "VIN 0,5; VDD 5V; Tamb=+125℃",
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