CD4070BM

{
  "slug": "cd4070bm",
  "version": "0.1.0",
  "type": "component",
  "description": "lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4070bm",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4070bm.kicad_sym",
    "cd4070bm.kicad_mod",
    "cd4070bm.glb",
    "cd4070bm.step",
    "cd4070bm.lbr",
    "docs/hero.png",
    "docs/cd4070bm-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4070bm-hero.glb",
    "cd4070bm-hero.overlay.json",
    "cd4070bm-etched.glb"
  ],
  "component": {
    "mpn": "CD4070BM",
    "manufacturer": "lingxingic",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388815683690496",
    "parts": {
      "symbol": "cd4070bm.kicad_sym",
      "footprint": "cd4070bm.kicad_mod",
      "model_3d": "cd4070bm-hero.glb",
      "model_3d_plain": "cd4070bm-etched.glb",
      "model_3d_step": "cd4070bm-etched.step",
      "model_3d_step_plain": "cd4070bm.step",
      "lbr": "cd4070bm.lbr"
    },
    "distributor_links": {
      "lcsc": "C32710662",
      "digikey": "296-14276-5-ND"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T17:22:53Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-14276-5-ND",
        "status": "found"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Data input for gate 1; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Data input for gate 1; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "3",
        "name": "1Y",
        "type": "output",
        "description": "Fully buffered data output of gate 1 (Y = A XOR B)."
      },
      {
        "number": "4",
        "name": "2Y",
        "type": "output",
        "description": "Fully buffered data output of gate 2 (Y = A XOR B)."
      },
      {
        "number": "5",
        "name": "2A",
        "type": "input",
        "description": "Data input for gate 2; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "6",
        "name": "2B",
        "type": "input",
        "description": "Data input for gate 2; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground (0 V) reference for the device; all voltages are referenced to VSS."
      },
      {
        "number": "8",
        "name": "3A",
        "type": "input",
        "description": "Data input for gate 3; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "9",
        "name": "3B",
        "type": "input",
        "description": "Data input for gate 3; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "10",
        "name": "3Y",
        "type": "output",
        "description": "Fully buffered data output of gate 3 (Y = A XOR B)."
      },
      {
        "number": "11",
        "name": "4Y",
        "type": "output",
        "description": "Fully buffered data output of gate 4 (Y = A XOR B)."
      },
      {
        "number": "12",
        "name": "4A",
        "type": "input",
        "description": "Data input for gate 4; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "13",
        "name": "4B",
        "type": "input",
        "description": "Data input for gate 4; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Supply voltage; recommended range 3 V to 15 V referenced to VSS, absolute maximum 18 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin configuration diagram on page 4 is an image with no text, so the pin mapping is taken from t; The ordering tables list CD4070BM alongside CD4070BE and CD4070PW, but do not explicitly map CD4070B; Output type for pins 3, 4, 10 and 11 is set to 'output' and pins 1, 2, 5, 6, 8, 9, 12 and 13 to 'inp"
        ],
        "pages_sent": 12,
        "cost_usd": 0.0436,
        "at": "2026-10-17T17:21:14"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388815683690496",
        "pages": 12,
        "sha256": "456878778715ecb0",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4070bm.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4070bm-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "b1920c44d56cee78f5f06b429f66f7657ffcb1c282e64c61df4a5da18dafd82b",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}