# CD4070BM

**lingxingic** · Logic Gates · SOP-14

CD4070BM from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input for gate 1; unused inputs must be connected to VDD, VSS, or another input. |
| 2 | 1B | input | Data input for gate 1; unused inputs must be connected to VDD, VSS, or another input. |
| 3 | 1Y | output | Fully buffered data output of gate 1 (Y = A XOR B). |
| 4 | 2Y | output | Fully buffered data output of gate 2 (Y = A XOR B). |
| 5 | 2A | input | Data input for gate 2; unused inputs must be connected to VDD, VSS, or another input. |
| 6 | 2B | input | Data input for gate 2; unused inputs must be connected to VDD, VSS, or another input. |
| 7 | VSS | power_in | Ground (0 V) reference for the device; all voltages are referenced to VSS. |
| 8 | 3A | input | Data input for gate 3; unused inputs must be connected to VDD, VSS, or another input. |
| 9 | 3B | input | Data input for gate 3; unused inputs must be connected to VDD, VSS, or another input. |
| 10 | 3Y | output | Fully buffered data output of gate 3 (Y = A XOR B). |
| 11 | 4Y | output | Fully buffered data output of gate 4 (Y = A XOR B). |
| 12 | 4A | input | Data input for gate 4; unused inputs must be connected to VDD, VSS, or another input. |
| 13 | 4B | input | Data input for gate 4; unused inputs must be connected to VDD, VSS, or another input. |
| 14 | VDD | power_in | Supply voltage; recommended range 3 V to 15 V referenced to VSS, absolute maximum 18 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VDD | -0.5 |  | 18 | V |  | 5 |
| DC input current | IIK | -10 |  | 10 | mA | any one input | 5 |
| input voltage | VI | -0.5 |  |  | V | all inputs | 5 |
| storage temperature | Tstg | -65 |  | 150 | ℃ |  | 5 |
| total power dissipation | Ptot |  |  | 500 | mW |  | 5 |
| device dissipation per output transistor | P |  |  | 100 | mW |  | 5 |
| supply voltage | VDD | 3 |  | 15 | V |  | 6 |
| ambient temperature | Tamb | -40 |  | 125 | ℃ | in free air | 6 |
| supply current | IDD |  |  | 1 | uA | VIN 0,5; VDD 5V; Tamb=25℃ | 6 |
| LOW-level output current | IOL | 0.51 | 1 |  | mA | VO 0.4; VIN 0,5; VDD 5V; Tamb=25℃ | 6 |
| LOW-level output current | IOL | 1.3 | 2.6 |  | mA | VO 0.5; VIN 0,10; VDD 10V; Tamb=25℃ | 6 |
| LOW-level output current | IOL | 3.4 | 6.8 |  | mA | VO 1.5; VIN 0,15; VDD 15V; Tamb=25℃ | 6 |
| HIGH-level output current | IOH | -0.51 | -1 |  | mA | VO 4.6; VIN 0,5; VDD 5V; Tamb=25℃ | 6 |
| HIGH-level output current | IOH | -1.6 | -3.2 |  | mA | VO 2.5; VIN 0,5; VDD 5V; Tamb=25℃ | 6 |
| HIGH-level output current | IOH | -1.3 | -2.6 |  | mA | VO 9.5; VIN 0,10; VDD 10V; Tamb=25℃ | 6 |
| HIGH-level output current | IOH | -3.4 | -6.8 |  | mA | VO 13.5; VIN 0,15; VDD 15V; Tamb=25℃ | 6 |
| LOW-level output voltage | VOL |  | 0 | 0.05 | V | VIN 0,5; VDD 5V; Tamb=25℃ | 6 |
| HIGH-level output voltage | VOH | 4.95 | 5 |  | V | VIN 0,5; VDD 5V; Tamb=25℃ | 6 |
| HIGH-level output voltage | VOH | 9.95 | 10 |  | V | VIN 0,10; VDD 10V; Tamb=25℃ | 6 |
| HIGH-level output voltage | VOH | 14.95 | 15 |  | V | VIN 0,15; VDD 15V; Tamb=25℃ | 6 |
| LOW-level input voltage | VIL |  |  | 1.5 | V | VO 0.5, 4.5; VDD 5V; Tamb=25℃ | 6 |
| LOW-level input voltage | VIL |  |  | 3 | V | VO 1, 9; VDD 10V; Tamb=25℃ | 6 |
| LOW-level input voltage | VIL |  |  | 4 | V | VO 1.5, 13.5; VDD 15V; Tamb=25℃ | 6 |
| HIGH-level input voltage | VIH | 3.5 |  |  | V | VO 0.5, 4.5; VDD 5V; Tamb=25℃ | 6 |
| HIGH-level input voltage | VIH | 7 |  |  | V | VO 1, 9; VDD 10V; Tamb=25℃ | 6 |
| HIGH-level input voltage | VIH | 11 |  |  | V | VO 1.5, 13.5; VDD 15V; Tamb=25℃ | 6 |
| input leakage current | II | -1 |  | 1 | uA | VIN 0,15; VDD 15V; Tamb=25℃ | 6 |
| supply current | IDD |  |  | 7.5 | uA | VIN 0,5; VDD 5V; Tamb=+125℃ | 7 |
| supply current | IDD |  |  | 15 | uA | VIN 0,10; VDD 10V; Tamb=+125℃ | 7 |
| supply current | IDD |  |  | 30 | uA | VIN 0,15; VDD 15V; Tamb=+125℃ | 7 |
| LOW-level output current | IOL | 0.36 |  |  | mA | VO 0.4; VIN 0,5; VDD 5V; Tamb=+125℃ | 7 |
| LOW-level output current | IOL | 0.9 |  |  | mA | VO 0.5; VIN 0,10; VDD 10V; Tamb=+125℃ | 7 |
| LOW-level output current | IOL | 2.4 |  |  | mA | VO 1.5; VIN 0,15; VDD 15V; Tamb=+125℃ | 7 |
| HIGH-level output current | IOH | -0.36 |  |  | mA | VO 4.6; VIN 0,5; VDD 5V; Tamb=+125℃ | 7 |
| HIGH-level output current | IOH | -1.15 |  |  | mA | VO 2.5; VIN 0,5; VDD 5V; Tamb=+125℃ | 7 |
| HIGH-level output current | IOH | -0.9 |  |  | mA | VO 9.5; VIN 0,10; VDD 10V; Tamb=+125℃ | 7 |
| HIGH-level output current | IOH | -2.4 |  |  | mA | VO 13.5; VIN 0,15; VDD 15V; Tamb=+125℃ | 7 |
| LOW-level output voltage | VOL |  |  | 0.05 | V | VIN 0,5; VDD 5V; Tamb=+125℃ | 7 |
| HIGH-level output voltage | VOH | 4.95 |  |  | V | VIN 0,5; VDD 5V; Tamb=+125℃ | 7 |
| HIGH-level output voltage | VOH | 9.95 |  |  | V | VIN 0,10; VDD 10V; Tamb=+125℃ | 7 |
| HIGH-level output voltage | VOH | 14.95 |  |  | V | VIN 0,15; VDD 15V; Tamb=+125℃ | 7 |
| LOW-level input voltage | VIL |  |  | 1.5 | V | VO 0.5, 4.5; VDD 5V; Tamb=+125℃ | 7 |
| LOW-level input voltage | VIL |  |  | 3 | V | VO 1, 9; VDD 10V; Tamb=+125℃ | 7 |
| LOW-level input voltage | VIL |  |  | 4 | V | VO 1.5, 13.5; VDD 15V; Tamb=+125℃ | 7 |
| HIGH-level input voltage | VIH | 3.5 |  |  | V | VO 0.5, 4.5; VDD 5V; Tamb=+125℃ | 7 |
| HIGH-level input voltage | VIH | 7 |  |  | V | VO 1, 9; VDD 10V; Tamb=+125℃ | 7 |
| HIGH-level input voltage | VIH | 11 |  |  | V | VO 1.5, 13.5; VDD 15V; Tamb=+125℃ | 7 |
| propagation delay time | tPHL, tPLH |  | 140 | 280 | ns | see Figure 4; VDD=5V; Tamb=25℃, tr,tf=20ns, CL=50pF, RL=200kΩ | 7 |
| propagation delay time | tPHL, tPLH |  | 65 | 130 | ns | see Figure 4; VDD=10V; Tamb=25℃, tr,tf=20ns, CL=50pF, RL=200kΩ | 7 |
| propagation delay time | tPHL, tPLH |  | 50 | 100 | ns | see Figure 4; VDD=15V; Tamb=25℃, tr,tf=20ns, CL=50pF, RL=200kΩ | 7 |
| transition time | tTHL, tTLH |  | 100 | 200 | ns | see Figure 4; VDD=5V; Tamb=25℃, tr,tf=20ns, CL=50pF, RL=200kΩ | 7 |
| transition time | tTHL, tTLH |  | 50 | 100 | ns | see Figure 4; VDD=10V; Tamb=25℃, tr,tf=20ns, CL=50pF, RL=200kΩ | 7 |
| transition time | tTHL, tTLH |  | 40 | 80 | ns | see Figure 4; VDD=15V; Tamb=25℃, tr,tf=20ns, CL=50pF, RL=200kΩ | 7 |
| input capacitance | CI |  | 5 | 7.5 | pF | any input; Tamb=25℃ | 7 |

## CAD (KiCad official)

- Symbol: `CD4070BM`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4070bm-etched.step` / `cd4070bm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4070bm.step` / `cd4070bm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388815683690496) (12 pp, sha256 `456878778715ecb0`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4070bm-datasheet.pdf)