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CD4070BD

Public Made by Adom

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Sungine Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4070BD

Sungine · Logic Gates · DIP-14

CD4070BD from Sungine, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Input A of gate J (J = A XOR B); inputs are clamped by protection diodes between VDD and VSS, with VIN range 0 to VDD.
2 B input Input B of gate J (J = A XOR B); inputs are clamped by protection diodes between VDD and VSS, with VIN range 0 to VDD.
3 J output Output of gate J = A XOR B, with symmetric source/sink drive capability.
4 K output Output of gate K = C XOR D, with symmetric source/sink drive capability.
5 C input Input C of gate K (K = C XOR D); inputs are clamped by protection diodes between VDD and VSS, with VIN range 0 to VDD.
6 D input Input D of gate K (K = C XOR D); inputs are clamped by protection diodes between VDD and VSS, with VIN range 0 to VDD.
7 VSS power_in Ground / negative supply (VSS = 0 V).
8 E input Input E of gate L (L = E XOR F); inputs are clamped by protection diodes between VDD and VSS, with VIN range 0 to VDD.
9 F input Input F of gate L (L = E XOR F); inputs are clamped by protection diodes between VDD and VSS, with VIN range 0 to VDD.
10 L output Output of gate L = E XOR F, with symmetric source/sink drive capability.
11 M output Output of gate M = G XOR H, with symmetric source/sink drive capability.
12 G input Input G of gate M (M = G XOR H); inputs are clamped by protection diodes between VDD and VSS, with VIN range 0 to VDD.
13 H input Input H of gate M (M = G XOR H); inputs are clamped by protection diodes between VDD and VSS, with VIN range 0 to VDD.
14 VDD power_in Positive supply voltage, recommended 3 V to 15 V (absolute maximum -0.5 to +18 V).

Key specifications

Parameter Value
Manufacturer Sungine
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 2
Input voltage VIN -0.5 V -0.5 ~ VDD+0.5 V 2
Storage temperature tS -65 150 °C 2
Power dissipation DIP PD 700 mW DIP 3
Soldering temperature tL 260 °C 10 s 3
Supply voltage VDD 3 15 V 3
Input voltage VIN 0 V 0 ~ VDD 3
Operating temperature tA -10 70 °C 3
Quiescent current, VDD=5V IDD 1 µA VDD=5V, VIN=VDD or VSS, 25°C 3
Quiescent current, VDD=10V IDD 2 µA VDD=10V, VIN=VDD or VSS, 25°C 3
Quiescent current, VDD=15V IDD 4 µA VDD=15V, VIN=VDD or VSS, 25°C 3
Quiescent current, VDD=15V, 85°C IDD 30 µA VDD=15V, VIN=VDD or VSS, 85°C 3
Low-level output voltage VOL 0.05 V /IO/<1µA, VDD=5V/10V/15V 3
High-level output voltage, VDD=5V VOH 4.95 V /IO/<1µA, VDD=5V 4
High-level output voltage, VDD=10V VOH 9.95 V /IO/<1µA, VDD=10V 4
High-level output voltage, VDD=15V VOH 14.95 V /IO/<1µA, VDD=15V 4
Low-level input voltage, VDD=5V VIL 1.5 V VDD=5V, VO=0.5V or 4.5V 4
Low-level input voltage, VDD=10V VIL 3 V VDD=10V, VO=1.0V or 9V 4
Low-level input voltage, VDD=15V VIL 4 V VDD=15V, VO=1.5V or 13.5V 4
High-level input voltage, VDD=5V VIH 3.5 V VDD=5V, VO=0.5V or 4.5V 4
High-level input voltage, VDD=10V VIH 7 V VDD=10V, VO=1.0V or 9.0V 4
High-level input voltage, VDD=15V VIH 11 V VDD=15V, VO=1.5V or 13.5V 4
Low-level output current, VDD=5V IOL 0.51 mA VDD=5V, VO=0.4V, 25°C 4
Low-level output current, VDD=10V IOL 1.3 mA VDD=10V, VO=0.5V, 25°C 4
Low-level output current, VDD=15V IOL 3.4 mA VDD=15V, VO=1.5V, 25°C 4
High-level output current, VDD=5V IOH -0.51 mA VDD=5V, VO=4.6V, 25°C 4
High-level output current, VDD=10V IOH -1.3 mA VDD=10V, VO=9.5V, 25°C 4
High-level output current, VDD=15V IOH -3.4 mA VDD=15V, VO=13.5V, 25°C 4
Input current IIN -0.3 0.3 µA VDD=15V, VIN=0V / 15V 4
Propagation delay, VDD=5V tPHL, tPLH 110 185 ns VDD=5V, TA=25°C, RL=200kΩ, CL=50pF 5
Propagation delay, VDD=10V tPHL, tPLH 50 90 ns VDD=10V, TA=25°C, RL=200kΩ, CL=50pF 5
Propagation delay, VDD=15V tPHL, tPLH 40 75 ns VDD=15V, TA=25°C, RL=200kΩ, CL=50pF 5
Transition time, VDD=5V tTHL, tTLH 100 200 ns VDD=5V, TA=25°C, RL=200kΩ, CL=50pF 5
Transition time, VDD=10V tTHL, tTLH 50 100 ns VDD=10V, TA=25°C, RL=200kΩ, CL=50pF 5
Transition time, VDD=15V tTHL, tTLH 40 80 ns VDD=15V, TA=25°C, RL=200kΩ, CL=50pF 5
Average input capacitance CIN 5 7.5 pF any input 5
Power dissipation capacitance CPD 20 pF any input 5

CAD (KiCad official)

  • Symbol: CD4070BD
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4070bd-etched.step / cd4070bd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4070bd.step / cd4070bd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Sungine datasheet (7 pp, sha256 af311194a420e1db, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF