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docs cd4069s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd4069s: viewers · Ray
cd4069s-etched.fit.json cd4069s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4069s-etched.glb cd4069s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4069s-etched.step cd4069s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd4069s.glb Publish 0.1.0 · Ray
cd4069s.kicad_mod Publish 0.1.0 · Ray
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cd4069s.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
page.json cd4069s: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md cd4069s: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CD4069S

GR · Inverters · SOP-14

CD4069S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Inverter 1 input. CMOS logic input; drives inverter 1 output Y1 (Y1 = /A1). Input current IIN ≤ 1 µA at VIN = VDD = 15 V.
2 Y1 output Inverter 1 output (Y1 = /A1). CMOS push-pull output; VOH ≈ VDD, VOL ≈ 0 V at
3 A2 input Inverter 2 input. CMOS logic input; drives inverter 2 output Y2 (Y2 = /A2).
4 Y2 output Inverter 2 output (Y2 = /A2). CMOS push-pull output.
5 A3 input Inverter 3 input. CMOS logic input; drives inverter 3 output Y3 (Y3 = /A3).
6 Y3 output Inverter 3 output (Y3 = /A3). CMOS push-pull output.
7 VSS power_in Negative supply / ground reference (0 V). All inputs and outputs are referenced to VSS.
8 Y4 output Inverter 4 output (Y4 = /A4). CMOS push-pull output.
9 A4 input Inverter 4 input. CMOS logic input; drives inverter 4 output Y4 (Y4 = /A4).
10 Y5 output Inverter 5 output (Y5 = /A5). CMOS push-pull output.
11 A5 input Inverter 5 input. CMOS logic input; drives inverter 5 output Y5 (Y5 = /A5).
12 Y6 output Inverter 6 output (Y6 = /A6). CMOS push-pull output.
13 A6 input Inverter 6 input. CMOS logic input; drives inverter 6 output Y6 (Y6 = /A6).
14 VDD power_in Positive supply rail. Recommended operating range 3.0 V to 15 V (absolute max 18 V). Quiescent supply current IDD ≤ 4 µA at VDD = 15 V, TA = 25 °C.

Key specifications

Parameter Value
Manufacturer GR
Package SOP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD4069SS
  • CD4069SD

CAD (KiCad official)

  • Symbol: CD4069S
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4069s-etched.step / cd4069s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4069s.step / cd4069s.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cd4069s.step 195 KB You want the bare part, or you mark your own boards.
cd4069s-etched.step 2.2 MB You want the part with CD4069S already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 534 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GR datasheet (5 pp, sha256 6889c8e2ce677e0f, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF