component

CD4069BM-TD

Public Made by Adom

by adom

TDSEMIC Inverters, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4069bm-tdfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cd4069bm-td / README.md
History Download
Ray Publish 0.1.0 47d79c6 5d ago

CD4069BM-TD

TDSEMIC · Inverters · SOP-14

CD4069BM-TD from TDSEMIC, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A1 input Channel 1 inverter input; unused inputs must be tied to VDD, VSS or another input, and input voltage range is -0.5 V to VDD+0.5 V.
2 Y1 output Channel 1 inverter output (Y = NOT A).
3 A2 input Channel 2 inverter input; unused inputs must be tied to VDD, VSS or another input, and input voltage range is -0.5 V to VDD+0.5 V.
4 Y2 output Channel 2 inverter output (Y = NOT A).
5 A3 input Channel 3 inverter input; unused inputs must be tied to VDD, VSS or another input, and input voltage range is -0.5 V to VDD+0.5 V.
6 Y3 output Channel 3 inverter output (Y = NOT A).
7 VSS power_in Negative supply, normally connected to ground (0 V reference for VDD).
8 Y4 output Channel 4 inverter output (Y = NOT A).
9 A4 input Channel 4 inverter input; unused inputs must be tied to VDD, VSS or another input, and input voltage range is -0.5 V to VDD+0.5 V.
10 Y5 output Channel 5 inverter output (Y = NOT A).
11 A5 input Channel 5 inverter input; unused inputs must be tied to VDD, VSS or another input, and input voltage range is -0.5 V to VDD+0.5 V.
12 Y6 output Channel 6 inverter output (Y = NOT A).
13 A6 input Channel 6 inverter input; unused inputs must be tied to VDD, VSS or another input, and input voltage range is -0.5 V to VDD+0.5 V.
14 VDD power_in Positive supply, recommended 3 V to 15 V (absolute maximum -0.5 V to 18 V referenced to VSS).

Key specifications

Parameter Value
Manufacturer TDSEMIC
Package SOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4069BM-TD
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4069bm-td-etched.step / cd4069bm-td-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4069bm-td.step / cd4069bm-td.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TDSEMIC datasheet (7 pp, sha256 1970137e739450d8, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF