CD4068BE

{
  "slug": "cd4068be",
  "version": "0.1.0",
  "type": "component",
  "description": "lingxingic Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4068be",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4068be.kicad_sym",
    "cd4068be.kicad_mod",
    "cd4068be.glb",
    "cd4068be.step",
    "cd4068be.lbr",
    "docs/hero.png",
    "docs/cd4068be-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4068be-hero.glb",
    "cd4068be-hero.overlay.json",
    "cd4068be-etched.glb"
  ],
  "component": {
    "mpn": "CD4068BE",
    "manufacturer": "lingxingic",
    "package": "DIP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388678584881152",
    "parts": {
      "symbol": "cd4068be.kicad_sym",
      "footprint": "cd4068be.kicad_mod",
      "model_3d": "cd4068be-hero.glb",
      "model_3d_plain": "cd4068be-etched.glb",
      "model_3d_step": "cd4068be-etched.step",
      "model_3d_step_plain": "cd4068be.step",
      "lbr": "cd4068be.lbr"
    },
    "distributor_links": {
      "lcsc": "C32710660",
      "digikey": "296-14124-5-ND",
      "mouser": "595-CD4068BE"
    },
    "distributor_check": {
      "checked_at": "2026-10-15T14:40:13Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-14124-5-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-CD4068BE",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "Y",
        "type": "output",
        "description": "Data output that gives the 8-input AND of inputs A to H, and the output is fully buffered."
      },
      {
        "number": "2",
        "name": "A",
        "type": "input",
        "description": "Data input A of the 8-input AND/NAND gate; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "3",
        "name": "B",
        "type": "input",
        "description": "Data input B of the 8-input AND/NAND gate; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "4",
        "name": "C",
        "type": "input",
        "description": "Data input C of the 8-input AND/NAND gate; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "5",
        "name": "D",
        "type": "input",
        "description": "Data input D of the 8-input AND/NAND gate; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "6",
        "name": "n.c.",
        "type": "unconnected",
        "description": "Not connected."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground (0 V), the reference for all voltages; the absolute maximum input voltage range is -0.5 V to VDD+0.5 V."
      },
      {
        "number": "8",
        "name": "n.c.",
        "type": "unconnected",
        "description": "Not connected."
      },
      {
        "number": "9",
        "name": "E",
        "type": "input",
        "description": "Data input E of the 8-input AND/NAND gate; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "10",
        "name": "F",
        "type": "input",
        "description": "Data input F of the 8-input AND/NAND gate; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "11",
        "name": "G",
        "type": "input",
        "description": "Data input G of the 8-input AND/NAND gate; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "12",
        "name": "H",
        "type": "input",
        "description": "Data input H of the 8-input AND/NAND gate; unused inputs must be connected to VDD, VSS, or another input."
      },
      {
        "number": "13",
        "name": "Y (complement)",
        "type": "output",
        "description": "Complement data output that gives the 8-input NAND of inputs A to H, and the output is fully buffered."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Supply voltage, recommended range 3 V to 15V referenced to VSS."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin configuration diagram (section 2.2, page 4) is an image and is not present in the extracted ; The datasheet covers DIP14, SOP14 and TSSOP14 with one shared pin table and no per-package pin map. ; Pin 14 is printed as VDD and pin 7 as VSS. Both are power pins with no separate signal function, so "
        ],
        "pages_sent": 12,
        "cost_usd": 0.0458,
        "at": "2026-10-15T14:39:56"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603388678584881152",
        "pages": 12,
        "sha256": "bd0186e1a9ad63e3",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cd4068be.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          19.05,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3dae072a95c64bee0d1e58be8e75383639f5017ab982de1749d05808a4eed058",
        "checked": "2026-10-15",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4068be-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
          7.874,
          19.05,
          6.98
        ],
        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "28f17447fe16fc819e379fbd1c45253b8b17f29af8967423bc966a18bc005fb1",
        "checked": "2026-10-15",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}