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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	cd4066bpwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	2mo ago
cd4066bpwr-etched.fit.json	cd4066bpwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
cd4066bpwr-etched.glb	cd4066bpwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray	15d ago
cd4066bpwr-etched.step	cd4066bpwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray	15d ago
cd4066bpwr.glb	Publish 0.1.0 · Ray	2mo ago
cd4066bpwr.kicad_mod	Publish 0.1.0 · Ray	2mo ago
cd4066bpwr.kicad_sym	Publish 0.1.0 · Ray	2mo ago
cd4066bpwr.lbr	rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray	2mo ago
cd4066bpwr.step	Publish 0.1.0 · Ray	2mo ago
package.json	Publish 0.2.0 · Ray	2mo ago
pads.json	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	2mo ago
page.json	cd4066bpwr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body… · Ray	15d ago
README.md	cd4066bpwr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	1mo ago

CD4066BPWR

Texas Instruments · Signal Switches / Encoders & Decoders / Multiplexers · TSSOP-14

CD4066BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SIG A IN/OUT	bidirectional	Bidirectional analog/digital signal terminal 1 of Switch A. Paired with pin 2 through the bilateral CMOS transmission gate; either terminal may serve as input or output. Signal path voltage must lie between VSS and VDD (3 V to 18 V range).
2	SIG A OUT/IN	bidirectional	Bidirectional analog/digital signal terminal 2 of Switch A. Connected to pin 1 through the bilateral CMOS transmission gate when CONTROL A (pin 13) is high.
3	SIG B OUT/IN	bidirectional	Bidirectional analog/digital signal terminal 2 of Switch B. Connected to pin 4 through the bilateral CMOS transmission gate when CONTROL B (pin 5) is high.
4	SIG B IN/OUT	bidirectional	Bidirectional analog/digital signal terminal 1 of Switch B. Paired with pin 3 through the bilateral CMOS transmission gate.
5	CONTROL B	input	Digital control input for Switch B. High (≥VIHC, typ 11 V at VDD=15 V) closes the switch; low (≤VILC=1 V) opens it. Very high input impedance (~10^12 Ω) isolates the control from the signal path.
6	CONTROL C	input	Digital control input for Switch C. High closes the switch, low opens it; input current typically < 1 µA over the recommended operating range.
7	VSS	power_in	Low-voltage power / analog reference. Typically ground for single-supply digital operation, or the negative rail for bipolar analog switching. Signal-path voltages must remain between VSS and VDD.
8	SIG C IN/OUT	bidirectional	Bidirectional analog/digital signal terminal 1 of Switch C. Paired with pin 9 through the bilateral CMOS transmission gate.
9	SIG C OUT/IN	bidirectional	Bidirectional analog/digital signal terminal 2 of Switch C. Connected to pin 8 through the bilateral CMOS transmission gate when CONTROL C (pin 6) is high.
10	SIG D OUT/IN	bidirectional	Bidirectional analog/digital signal terminal 2 of Switch D. Connected to pin 11 through the bilateral CMOS transmission gate when CONTROL D (pin 12) is high.
11	SIG D IN/OUT	bidirectional	Bidirectional analog/digital signal terminal 1 of Switch D. Paired with pin 10 through the bilateral CMOS transmission gate.
12	CONTROL D	input	Digital control input for Switch D. High (≥VIHC) closes the switch between pins 10 and 11; low (≤VILC=1 V) opens it.
13	CONTROL A	input	Digital control input for Switch A. High closes the switch between pins 1 and 2; low opens it. Input is isolated from the signal path (typ 10^12 Ω).
14	VDD	power_in	Positive supply pin. Recommended VDD 3 V to 18 V (absolute max 20 V referenced to VSS). Also sets the logic-high threshold for the CONTROL inputs and the upper rail of the analog signal path.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-14
Category	Logic
Pins	14

Ordering variants

Same part, different packaging or reel option.

CD4066BPWR
CD4066BPWRN
CD4066BPWRD
CD4066BPWRNS

CAD (KiCad official)

Symbol: CD4066BPWR
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: cd4066bpwr-etched.step / cd4066bpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4066bpwr.step / cd4066bpwr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`cd4066bpwr.step`	194 KB	You want the bare part, or you mark your own boards.
`cd4066bpwr-etched.step`	2.6 MB	You want the part with `CD4066BPWR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 645 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 4f32edb6ac586cfb, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF