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CD4060S
Public Made by Adomby adom
GR Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4060S
GR · Counters, Dividers · SOP-16
CD4060S from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Counter output Q12 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 2 | Q13 | output | Counter output Q13 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 3 | Q14 | output | Counter output Q14 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 4 | Q6 | output | Counter output Q6 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 5 | Q5 | output | Counter output Q5 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 6 | Q7 | output | Counter output Q7 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 7 | Q4 | output | Counter output Q4 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 8 | VSS | power_in | Power ground (电源地); the reference for the stated supply range VDD-VSS of 3 V to 15 V. |
| 9 | ФO | output | Clock output (时钟输出端) from the internal oscillator stage, whose falling edge clocks the counter. |
| 10 | ФO (inverted) | output | Inverted clock output (时钟反相输出端), the complement of pin 9. |
| 11 | ФI | input | Clock input (时钟输入端) for external RC or crystal oscillator configuration; the clock line uses a Schmitt trigger to limit rise and fall times. |
| 12 | RESET | input | Reset input (清零端); when held high the counter is cleared and the oscillator is disabled. |
| 13 | Q9 | output | Counter output Q9 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 14 | Q8 | output | Counter output Q8 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 15 | Q10 | output | Counter output Q10 of the 14-bit binary counter, which advances on the falling edge of the clock (ФO). |
| 16 | VDD | power_in | Positive supply (电源正); operating range VDD-VSS 3 V to 15 V, absolute maximum 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage | VDD-VSS | -0.5 | 18 | V | 2 | ||
| Analog supply voltage | VDD-VEE | 18 | V | 2 | |||
| DC input voltage | VIN | -0.5 | V | Printed as -0.5+VSS ~ VDD+0.5V; min is -0.5 relative to VSS, max printed only as VDD+0.5V | 2 | ||
| Power dissipation | PD | 500 | mW | 2 | |||
| Operating temperature | TA | 0 | 70 | ℃ | 2 | ||
| Storage temperature | TS | -65 | 150 | ℃ | 2 | ||
| Lead soldering temperature | TW | 260 | ℃ | 10 s | 2 | ||
| DC supply voltage | VDD-VSS | 3 | 15 | V | 3 | ||
| Control input voltage | VIS | 0 | V | Upper limit printed as VDD-VSS | 3 | ||
| Analog supply voltage | VDD-VEE | 0 | 15 | V | 3 | ||
| Analog input/output voltage | VIN、VOUT | 0 | V | Upper limit printed as VDD-VEE | 3 | ||
| Operating temperature | TA | 0 | 60 | ℃ | 3 | ||
| High-level input voltage | VIH | 3.5 | V | TA=25℃; /IO/≤1uA; Vo=0.5V; VDD=5V | 3 | ||
| High-level input voltage | VIH | 7 | V | TA=25℃; /IO/≤1uA; Vo=1V; VDD=10V | 3 | ||
| High-level input voltage | VIH | 11 | V | TA=25℃; /IO/≤1uA; Vo=1.5V; VDD=15V | 3 | ||
| Low-level input voltage | VIL | 1.5 | V | TA=25℃; /IO/≤1uA; Vo=4.5V; VDD=5V | 3 | ||
| Low-level input voltage | VIL | 3 | V | TA=25℃; /IO/≤1uA; Vo=9V; VDD=10V | 3 | ||
| Low-level input voltage | VIL | 4 | V | TA=25℃; /IO/≤1uA; Vo=13.5V; VDD=15V | 3 | ||
| High-level output voltage | VOH | 4.95 | V | TA=25℃; /IOUT/<1uA; VDD=5V | 3 | ||
| High-level output voltage | VOH | 9.95 | V | TA=25℃; /IOUT/<1uA; VDD=10V | 3 | ||
| High-level output voltage | VOH | 14.95 | V | TA=25℃; /IOUT/<1uA; VDD=15V | 3 | ||
| Low-level output voltage | VOL | 0.05 | V | TA=25℃; /IOUT/<1uA; VDD=5V | 3 | ||
| Input current | IIN | 0.01 | 1 | uA | TA=25℃; VIN=VDD or VSS; VDD=15V | 3 | |
| High-level output current | IOH | -1.1 | mA | TA=25℃; Vo=4.6V; VDD=5V | 3 | ||
| High-level output current | IOH | -2.3 | mA | TA=25℃; Vo=9.5V; VDD=10V | 3 | ||
| High-level output current | IOH | -8.5 | mA | TA=25℃; Vo=13.5V; VDD=15V | 3 | ||
| Low-level output current | IOL | 2.2 | mA | TA=25℃; Vo=0.4V; VDD=5V | 3 | ||
| Low-level output current | IOL | 5.1 | mA | TA=25℃; Vo=0.5V; VDD=10V | 3 | ||
| Low-level output current | IOL | 19 | mA | TA=25℃; Vo=1.5V; VDD=15V | 3 | ||
| Operating current | IDD | 0.1 | 5 | uA | TA=25℃; VIN=VDD or VSS; VDD=5V | 3 | |
| Operating current | IDD | 0.1 | 10 | uA | TA=25℃; VIN=VDD or VSS; VDD=10V | 3 | |
| Operating current | IDD | 0.1 | 20 | uA | TA=25℃; VIN=VDD or VSS; VDD=15V | 3 | |
| Maximum propagation delay time RESET to Q (high-to-low) | tPHL | 140 | ns | Ta=25℃; RL=200k; CL=51pF; VDD=5V | 3 | ||
| Maximum propagation delay time RESET to Q (low-to-high) | tPLH | 400 | ns | Ta=25℃; RL=200k; CL=51pF; VDD=5V | 3 | ||
| Maximum propagation delay time RESET to Q (high-to-low) | tPHL | 190 | ns | Ta=25℃; RL=200k; CL=51pF; VDD=10V | 3 | ||
| Maximum propagation delay time RESET to Q (low-to-high) | tPLH | 230 | ns | Ta=25℃; RL=200k; CL=51pF; VDD=10V | 3 | ||
| Maximum propagation delay time RESET to Q (high-to-low) | tPHL | 170 | ns | Ta=25℃; RL=200k; CL=51pF; VDD=15V | 3 | ||
| Maximum propagation delay time RESET to Q (low-to-high) | tPLH | 190 | ns | Ta=25℃; RL=200k; CL=51pF; VDD=15V | 3 |
CAD (KiCad official)
- Symbol:
CD4060S - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4060s-etched.step/cd4060s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4060s.step/cd4060s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (5 pp, sha256
72cdabaff03d47bf, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).