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Contents

README

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CD4060BPWR

Texas Instruments · Counters, Dividers · TSSOP-16

CD4060BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q12 output Buffered ripple-carry counter output Q12 (2^12 divider stage); toggles on the negative transition of the input clock (phi-I/phi-O) and is forced low by RESET.
2 Q13 output Buffered ripple-carry counter output Q13 (2^13 divider stage); toggles on the negative transition of the input clock and is forced low by RESET.
3 Q14 output Buffered ripple-carry counter output Q14 (2^14 divider stage, highest-order output shown separately in the logic diagram); toggles on the negative transition of the input clock and is forced low by RESET.
4 Q6 output Buffered ripple-carry counter output Q6 (2^6 divider stage); toggles on the negative transition of the input clock and is forced low by RESET.
5 Q5 output Buffered ripple-carry counter output Q5 (2^5 divider stage); toggles on the negative transition of the input clock and is forced low by RESET.
6 Q7 output Buffered ripple-carry counter output Q7 (2^7 divider stage); toggles on the negative transition of the input clock and is forced low by RESET.
7 Q4 output Buffered ripple-carry counter output Q4 (2^4 divider stage); toggles on the negative transition of the input clock and is forced low by RESET.
8 VSS power_in Negative supply/ground reference terminal; all device voltages, including the -0.5V to +20V VDD supply range, are referenced to this pin.
9 φO output Oscillator output (phi-O), fed back through the external RC or crystal network to phi-I to complete the on-chip Schmitt-trigger oscillator; the counter also advances on its negative transition.
10 φO (bar) output Complementary oscillator output (inverted phi-O) used together with pin 9 for connecting the external crystal or RC feedback network in the oscillator configuration.
11 φI input Schmitt-trigger buffered oscillator/clock input; the counter advances one binary count on each negative-going transition of phi-I (and phi-O), and Schmitt action permits unlimited input-pulse rise and fall times.
12 R (RESET) input Active-high RESET input; a high level resets all counter stages to the all-0's state and disables the oscillator, and R=HIGH dominates over clocking.
13 Q9 output Buffered ripple-carry counter output Q9 (2^9 divider stage); toggles on the negative transition of the input clock and is forced low by RESET.
14 Q8 output Buffered ripple-carry counter output Q8 (2^8 divider stage); toggles on the negative transition of the input clock and is forced low by RESET.
15 Q10 output Buffered ripple-carry counter output Q10 (2^10 divider stage); toggles on the negative transition of the input clock and is forced low by RESET.
16 VDD power_in Positive supply voltage input; recommended supply range is 3V to 18V and absolute maximum DC supply-voltage range is -0.5V to +20V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4060BPWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4060bpwr-etched.step / cd4060bpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4060bpwr.step / cd4060bpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 393cbd8ba22d5db0, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-5 (text+vision), consensus claude-opus-4-8 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF