Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

CD4060BM-TD

TDSEMIC · Counters, Dividers · SOP-16

CD4060BM-TD from TDSEMIC, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q12 output 14-bit binary ripple counter stage 12 output.
2 Q13 output 14-bit binary ripple counter stage 13 output.
3 Q14 output 14-bit binary ripple counter stage 14 output.
4 Q6 output 14-bit binary ripple counter stage 6 output.
5 Q5 output 14-bit binary ripple counter stage 5 output.
6 Q7 output 14-bit binary ripple counter stage 7 output.
7 Q4 output 14-bit binary ripple counter stage 4 output (lowest-order output brought out).
8 VSS power_in Ground (0 V) supply reference.
9 ~{Φ0} output Oscillator driver output terminal 1 (振荡器驱动输出端1); output of internal inverter for RC/crystal oscillator network.
10 Φ0 passive Oscillator driver output terminal 2 (振荡器驱动输出端2); feedback/series-resistor RS connection point of the on-chip oscillator network.
11 Φ1 input Oscillator driver input terminal (振荡器驱动输入端); input of internal oscillator inverter or direct external clock input, maximum 12 MHz at 15 V.
12 RESET input Asynchronous master reset, active high (复位,高电平复位); forces all 14 counter stages and oscillator to 0 when driven high.
13 Q9 output 14-bit binary ripple counter stage 9 output.
14 Q8 output 14-bit binary ripple counter stage 8 output.
15 Q10 output 14-bit binary ripple counter stage 10 output.
16 VDD power_in Positive supply voltage; recommended 2.0 V (min) to 20 V (max), absolute maximum +20 V; parameters evaluated at 5 V, 10 V, and 15 V.

Key specifications

Parameter Value
Manufacturer TDSEMIC
Package SOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4060BM-TD
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4060bm-td-etched.step / cd4060bm-td-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4060bm-td.step / cd4060bm-td.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TDSEMIC datasheet (5 pp, sha256 7ecd20bd1a363654, retrieved 2026-09-29, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF