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Contents

README

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CD4060BE

HGSEMI · Counters / Dividers · DIP-16

CD4060BE from HGSEMI, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q12 output Buffered output of counter stage 12 (divide-by-4096 of the oscillator). CMOS push-pull output driven from VSS to VDD.
2 Q13 output Buffered output of counter stage 13 (divide-by-8192). CMOS push-pull output.
3 Q14 output Buffered output of counter stage 14 (divide-by-16384). CMOS push-pull output.
4 Q6 output Buffered output of counter stage 6 (divide-by-64). CMOS push-pull output.
5 Q5 output Buffered output of counter stage 5 (divide-by-32). CMOS push-pull output.
6 Q7 output Buffered output of counter stage 7 (divide-by-128). CMOS push-pull output.
7 Q4 output Buffered output of counter stage 4 (divide-by-16). CMOS push-pull output.
8 VSS power_in Negative supply / ground reference (0 V). Connect to system ground.
9 RS output RC oscillator feedback / inverter output. In RC mode it drives the RC network; in crystal mode it drives the crystal feedback loop. Also usable as the oscillator buffer output.
10 CTC input Oscillator input from RC or crystal network. Together with pins 9 and 11 forms the on-chip oscillator; can also accept an external clock when the internal oscillator is not used.
11 RTC input Oscillator timing-resistor node. Ties to the timing resistor Rt in an RC oscillator; participates in the feedback loop for a crystal oscillator.
12 MR input Master reset (active HIGH). A HIGH level asynchronously clears all 14 counter stages and forces buffered outputs LOW; must be held LOW for normal counting.
13 Q9 output Buffered output of counter stage 9 (divide-by-512). CMOS push-pull output.
14 Q8 output Buffered output of counter stage 8 (divide-by-256). CMOS push-pull output.
15 Q10 output Buffered output of counter stage 10 (divide-by-1024). CMOS push-pull output.
16 VDD power_in Positive supply voltage. Recommended operating range 3 V to 18 V; bypass locally with a 0.1 µF ceramic capacitor to VSS.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package DIP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • CD4060BE

CAD (KiCad official)

  • Symbol: CD4060BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4060be-etched.step / cd4060be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4060be.step / cd4060be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (10 pp, sha256 a7261cab2fab8294, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF