component

CD4060B 14-Stage Counter

Public Made by Adom

by adom

14-stage ripple-carry binary counter with an on-chip oscillator, 3 V to 18 V.

logiccounterripple-counteroscillator4000-seriestisoic-16
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Made with kicad-footprint-generator 10.0 · KiCad file format 20260206
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docs cd4060: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers interactive viewers · Ray 2mo ago
cd4060-etched.fit.json cd4060: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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CD4060B.adom-lbr.json CD4060B: validated Fusion/EAGLE library + adom-lbr hub, generated from this page's KiCad sources · Ray 2mo ago
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CD4060B

Texas Instruments · Counter · SOIC-16

The CD4060B is a 14-stage ripple-carry binary counter with an integrated oscillator that needs only an external crystal or RC network to run. It divides the oscillator down through stages Q4 to Q14, making it a common way to generate long time delays and slow clocks in the 3 V to 18 V range.

Pinout

Pin Name Type Function
1 Q12 output Buffered counter output from the 12th ripple stage (input frequency divided by 2^12 = 4096). CMOS output swings between VSS and VDD; sink/source ~1 mA at VDD=5 V. Held low while RESET is high.
2 Q13 output Buffered counter output from the 13th ripple stage (÷8192). CMOS rail-to-rail output; sink/source ~1 mA at VDD=5 V. Forced low by RESET.
3 Q14 output Buffered counter output from the 14th (final) ripple stage (÷16384). CMOS rail-to-rail output; sink/source ~1 mA at VDD=5 V. Forced low by RESET.
4 Q6 output Buffered counter output from the 6th ripple stage (÷64). CMOS rail-to-rail output. Forced low by RESET.
5 Q5 output Buffered counter output from the 5th ripple stage (÷32). CMOS rail-to-rail output. Forced low by RESET.
6 Q7 output Buffered counter output from the 7th ripple stage (÷128). CMOS rail-to-rail output. Forced low by RESET.
7 Q4 output Buffered counter output from the 4th ripple stage (÷16). CMOS rail-to-rail output. Forced low by RESET.
8 VSS power_in Negative supply / ground reference for the device. Typically tied to 0 V.
9 PhiO output Oscillator output (phi_O). Buffered non-inverted oscillator waveform; used with an external RC (Rx, Cx) or crystal network to close the oscillator loop. Also serves as the counter clock input to the first divider stage.
10 PhiO_bar output Complemented oscillator output (phi_O with overbar). Buffered inverted oscillator waveform used with the external RC or crystal timing network.
11 PhiI input Oscillator / external clock input (phi_I). In RC or crystal mode this is one node of the timing network; in external-clock mode a CMOS pulse train is driven into this pin. Schmitt-trigger input permits unlimited input rise/fall times. Counter advances one step on each negative-going (HIGH-to-LOW) transition at phi_I.
12 RESET input Active-high asynchronous master reset. A HIGH level clears every counter stage (Q1-Q14) to 0 and disables the oscillator. Must be returned LOW for normal counting. Minimum reset pulse width 60/30/20 ns at VDD=5/10/15 V.
13 Q9 output Buffered counter output from the 9th ripple stage (÷512). CMOS rail-to-rail output. Forced low by RESET.
14 Q8 output Buffered counter output from the 8th ripple stage (÷256). CMOS rail-to-rail output. Forced low by RESET.
15 Q10 output Buffered counter output from the 10th ripple stage (÷1024). CMOS rail-to-rail output. Forced low by RESET.
16 VDD power_in Positive supply. Recommended operating range 3 V to 18 V (parametric ratings given at 5, 10 and 15 V); absolute maximum 20 V referenced to VSS.

Key specifications

Parameter Value
Type 14-stage ripple binary counter + oscillator
Logic family 4000B (CMOS)
Available outputs Q4 through Q14 (stages 1-3 not pinned out)
Oscillator On-chip (crystal or RC)
Supply voltage 3 V to 18 V
Operating temperature -55 C to 125 C

Ordering variants

Same part, different packaging or reel option.

  • CD4060BBM
  • CD4060BBM96
  • CD4060BBM96E4
  • CD4060BBM96G4
  • CD4060BBME4
  • CD4060BBMG4
  • CD4060BBMT
  • CD4060BBMTE4
  • CD4060BBMTG4
  • CD4060BBE
  • CD4060BBEE4
  • CD4060BBF
  • CD4060BBF3A
  • CD4060BBF3AS2534
  • CD4060BBNSR
  • CD4060BBNSRE4
  • CD4060BBNSRG4
  • CD4060BBPW
  • CD4060BBPWE4
  • CD4060BBPWG4
  • CD4060BBPWR
  • CD4060BBPWRE4
  • CD4060BBPWRG4

CAD (KiCad official)

  • Symbol: cd4060.kicad_sym
  • Footprint: cd4060.kicad_mod
  • 3D model: SOIC-16 body from KiCad Package_SO/SOIC-16_3.9x9.9mm_P1.27mm.
  • 3D model files: cd4060-etched.step / cd4060-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4060.step / cd4060.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 1797bd648b653771, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF