component
CD4060B 14-Stage Counter
Public Made by Adomby adom
14-stage ripple-carry binary counter with an on-chip oscillator, 3 V to 18 V.
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page.json+167−8@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4060",+ "title": "CD4060B 14-Stage Counter",+ "brief": "14-stage ripple-carry binary counter with an on-chip oscillator, 3 V to 18 V.", "version": "0.1.0",- "type": "component",- "description": "14-stage ripple-carry binary counter with an on-chip oscillator, 3 V to 18 V.",+ "license": "CC-BY-SA-4.0", "tags": [ "logic", "counter",@@ -12,6 +15,167 @@ "ti", "soic-16" ],+ "component": {+ "mpn": "CD4060B",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counter",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd4060b.pdf",+ "parts": {+ "symbol": "cd4060.kicad_sym",+ "footprint": "cd4060.kicad_mod",+ "model_3d": "cd4060.glb"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "Q12",+ "type": "output",+ "description": "Buffered counter output from the 12th ripple stage (input frequency divided by 2^12 = 4096). CMOS output swings between VSS and VDD; sink/source ~1 mA at VDD=5 V. Held low while RESET is high."+ },+ {+ "number": "2",+ "name": "Q13",+ "type": "output",+ "description": "Buffered counter output from the 13th ripple stage (\u00f78192). CMOS rail-to-rail output; sink/source ~1 mA at VDD=5 V. Forced low by RESET."+ },+ {+ "number": "3",+ "name": "Q14",+ "type": "output",+ "description": "Buffered counter output from the 14th (final) ripple stage (\u00f716384). CMOS rail-to-rail output; sink/source ~1 mA at VDD=5 V. Forced low by RESET."+ },+ {+ "number": "4",+ "name": "Q6",+ "type": "output",+ "description": "Buffered counter output from the 6th ripple stage (\u00f764). CMOS rail-to-rail output. Forced low by RESET."+ },+ {+ "number": "5",+ "name": "Q5",+ "type": "output",+ "description": "Buffered counter output from the 5th ripple stage (\u00f732). CMOS rail-to-rail output. Forced low by RESET."+ },+ {+ "number": "6",+ "name": "Q7",+ "type": "output",+ "description": "Buffered counter output from the 7th ripple stage (\u00f7128). CMOS rail-to-rail output. Forced low by RESET."+ },+ {+ "number": "7",+ "name": "Q4",+ "type": "output",+ "description": "Buffered counter output from the 4th ripple stage (\u00f716). CMOS rail-to-rail output. Forced low by RESET."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply / ground reference for the device. Typically tied to 0 V."+ },+ {+ "number": "9",+ "name": "PhiO",+ "type": "output",+ "description": "Oscillator output (phi_O). Buffered non-inverted oscillator waveform; used with an external RC (Rx, Cx) or crystal network to close the oscillator loop. Also serves as the counter clock input to the first divider stage."+ },+ {+ "number": "10",+ "name": "PhiO_bar",+ "type": "output",+ "description": "Complemented oscillator output (phi_O with overbar). Buffered inverted oscillator waveform used with the external RC or crystal timing network."+ },+ {+ "number": "11",+ "name": "PhiI",+ "type": "input",+ "description": "Oscillator / external clock input (phi_I). In RC or crystal mode this is one node of the timing network; in external-clock mode a CMOS pulse train is driven into this pin. Schmitt-trigger input permits unlimited input rise/fall times. Counter advances one step on each negative-going (HIGH-to-LOW) transition at phi_I."+ },+ {+ "number": "12",+ "name": "RESET",+ "type": "input",+ "description": "Active-high asynchronous master reset. A HIGH level clears every counter stage (Q1-Q14) to 0 and disables the oscillator. Must be returned LOW for normal counting. Minimum reset pulse width 60/30/20 ns at VDD=5/10/15 V."+ },+ {+ "number": "13",+ "name": "Q9",+ "type": "output",+ "description": "Buffered counter output from the 9th ripple stage (\u00f7512). CMOS rail-to-rail output. Forced low by RESET."+ },+ {+ "number": "14",+ "name": "Q8",+ "type": "output",+ "description": "Buffered counter output from the 8th ripple stage (\u00f7256). CMOS rail-to-rail output. Forced low by RESET."+ },+ {+ "number": "15",+ "name": "Q10",+ "type": "output",+ "description": "Buffered counter output from the 10th ripple stage (\u00f71024). CMOS rail-to-rail output. Forced low by RESET."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply. Recommended operating range 3 V to 18 V (parametric ratings given at 5, 10 and 15 V); absolute maximum 20 V referenced to VSS."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd4060b.pdf",+ "pages": 29,+ "sha256": "1797bd648b653771",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Type": "14-stage ripple binary counter + oscillator",+ "Logic family": "4000B (CMOS)",+ "Available outputs": "Q4 through Q14 (stages 1-3 not pinned out)",+ "Oscillator": "On-chip (crystal or RC)",+ "Supply voltage": "3 V to 18 V",+ "Operating temperature": "-55 C to 125 C"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "binary counter",+ "timer divider",+ "long time delay",+ "RC oscillator counter"+ ],+ "discovery_pitch": "A 14-stage counter with a built-in oscillator: add a crystal or RC and get clean divided-down timing for long delays.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -27,10 +191,5 @@ "docs/cd4060-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }