component
CD4053S
Public Made by Adomby adom
GR Analog Switches, Multiplexers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4053S
GR · Analog Switches, Multiplexers · SOP-16
CD4053S from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | by | passive | Analog switch channel terminal 'by', which conducts to common terminal b when INH is low and the control inputs select the y side per the truth table. |
| 2 | bx | passive | Analog switch channel terminal 'bx', which conducts to common terminal b when INH is low and the control inputs select the x side per the truth table. |
| 3 | cy | passive | Analog switch channel terminal 'cy', which conducts to common terminal c when INH is low and the C control input selects the y side. |
| 4 | cx OR cy | passive | Common terminal c of the 'c' switch pair, connected to either cx or cy depending on the C control input. |
| 5 | cx | passive | Analog switch channel terminal 'cx', which conducts to common terminal c when INH is low and the C control input selects the x side. |
| 6 | INH | input | Inhibit (enable) control input; when high (logic 1) all channels are turned off, regardless of A, B and C, per the truth table. |
| 7 | VEE | power_in | Analog switch negative supply; the recommended analog supply range is VDD-VEE 0 to 15 V. |
| 8 | VSS | power_in | Digital supply ground (0 V reference) for the channel control inputs; control input voltage is specified relative to VSS. |
| 9 | C | input | Channel control input for the c switch pair, selecting the x path (logic 0) or the y path (logic 1) when INH is low; the control input range is 0 to VDD-VSS. |
| 10 | B | input | Channel control input for the b switch pair, selecting the x path (logic 0) or the y path (logic 1) when INH is low; the control input range is 0 to VDD-VSS. |
| 11 | A | input | Channel control input for the a switch pair, selecting the x path (logic 0) or the y path (logic 1) when INH is low; the control input range is 0 to VDD-VSS. |
| 12 | ax | passive | Analog switch channel terminal 'ax', which conducts to common terminal a when INH is low and the A control input selects the x side. |
| 13 | ay | passive | Analog switch channel terminal 'ay', which conducts to common terminal a when INH is low and the A control input selects the y side. |
| 14 | ax OR ay | passive | Common terminal a of the 'a' switch pair, connected to either ax or ay depending on the A control input. |
| 15 | bx OR by | passive | Common terminal b of the 'b' switch pair, connected to either bx or by depending on the B control input. |
| 16 | VDD | power_in | Positive supply; the recommended VDD-VSS range is 3 V to 15 V, with an absolute maximum of 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage (recommended) | VDD-VSS | 3 | 15 | V | 3 | ||
| Analog supply voltage (recommended) | VDD-VEE | 0 | 15 | V | 3 | ||
| Control input voltage (recommended) | VIS | 0 | V | 3 | |||
| Analog input/output voltage (recommended) | VIN, VOUT | 0 | V | 3 | |||
| Operating temperature (recommended) | TA | 0 | 60 | ℃ | 3 | ||
| DC supply voltage (absolute maximum) | VDD-VSS | -0.5 | 18 | V | 2 | ||
| Analog supply voltage (absolute maximum) | VDD-VEE | 18 | V | 2 | |||
| DC input voltage (absolute maximum) | VIN | -0.5 | V | min printed as -0.5+VSS; max printed as VDD+0.5 V | 2 | ||
| Power dissipation (absolute maximum) | PD | 500 | mW | 2 | |||
| Operating temperature (absolute maximum) | TA | 0 | 70 | ℃ | 2 | ||
| Storage temperature (absolute maximum) | TS | -65 | 150 | ℃ | 2 | ||
| Lead soldering temperature (absolute maximum) | TW | 260 | ℃ | 10 s | 2 | ||
| High-level input voltage | VIH | 3.5 | V | VDD=5 V; VIH=VDD through 1k; VEE=VSS; RL=1kΩ to VSS; IIS<2uA on all OFF channels | 3 | ||
| High-level input voltage | VIH | 7 | V | VDD=10 V; VIH=VDD through 1k; VEE=VSS; RL=1kΩ to VSS; IIS<2uA on all OFF channels | 3 | ||
| High-level input voltage | VIH | 11 | V | VDD=15 V; VIH=VDD through 1k; VEE=VSS; RL=1kΩ to VSS; IIS<2uA on all OFF channels | 3 | ||
| Low-level input voltage | VIL | 1.5 | V | VDD=5 V; VIL=VDD through 1k | 3 | ||
| Low-level input voltage | VIL | 3 | V | VDD=10 V; VIL=VDD through 1k | 3 | ||
| Low-level input voltage | VIL | 4 | V | VDD=15 V; VIL=VDD through 1k | 3 | ||
| Channel OFF leakage current | IOFF | -100 | 100 | nA | VDD=18 V; input/output channels OFF, INH=VDD | 3 | |
| Input current | IIN | -0.1 | 0.01 | 0.1 | uA | VDD=18 V; VIN=VDD or VSS | 3 |
| Quiescent supply current | IDD | 0.01 | 5 | uA | VDD=5 V; VIN=VDD or VSS | 3 | |
| Quiescent supply current | IDD | 0.01 | 10 | uA | VDD=10 V; VIN=VDD or VSS | 3 | |
| Quiescent supply current | IDD | 0.01 | 20 | uA | VDD=15 V; VIN=VDD or VSS | 3 |
CAD (KiCad official)
- Symbol:
CD4053S - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4053s-etched.step/cd4053s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4053s.step/cd4053s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (5 pp, sha256
f222f0f67d915a35, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).