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CD4053BM-MS

Public Made by Adom

by adom

MSKSEMI Analog Switches, Multiplexers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4053BM-MS

MSKSEMI · Analog Switches, Multiplexers · SOP-16

CD4053BM-MS from MSKSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 by passive Analog switch terminal of channel y (b-side) of the 3-channel dual-throughput multiplexer, passing signal to common pin 15 when selected; analog voltage range is 0 to VDD-VEE.
2 bx passive Analog switch terminal of channel x (b-side), passing signal to common pin 15 when selected; analog voltage range is 0 to VDD-VEE.
3 cy passive Analog switch terminal of channel y (c-side), passing signal to common pin 4 when selected; analog voltage range is 0 to VDD-VEE.
4 cx/cy passive Common analog terminal for the c switch pair (cx OR cy), connected to whichever channel terminal is selected by the A/B/C address inputs.
5 cx passive Analog switch terminal of channel x (c-side), passing signal to common pin 4 when selected; analog voltage range is 0 to VDD-VEE.
6 INH input Inhibit (enable) control input; when INH is high (1) all channels are turned off regardless of A, B and C, and the recommended control input range is 0 to VDD-VSS.
7 VEE power_in Negative analog supply for the analog switches; recommended analog supply VDD-VEE is 0 to 15 V and the absolute maximum is 18 V.
8 VSS power_in Digital ground and logic reference for the control inputs; recommended VDD-VSS is 3 V to 15 V and the absolute maximum is -0.5 V to 18 V.
9 C input Channel-select control input C, selecting between the x and y channel of the c switch pair together with A and B; control levels are referenced to VSS.
10 B input Channel-select control input B, selecting between the x and y channel of the b switch pair together with A and C; control levels are referenced to VSS.
11 A input Channel-select control input A, selecting between the x and y channel of the a switch pair together with B and C; control levels are referenced to VSS.
12 ax passive Analog switch terminal of channel x (a-side), passing signal to common pin 14 when selected; analog voltage range is 0 to VDD-VEE.
13 ay passive Analog switch terminal of channel y (a-side), passing signal to common pin 14 when selected; analog voltage range is 0 to VDD-VEE.
14 ax/ay passive Common analog terminal for the a switch pair (ax OR ay), connected to whichever channel terminal is selected by the A/B/C address inputs.
15 bx/by passive Common analog terminal for the b switch pair (bx OR by), connected to whichever channel terminal is selected by the A/B/C address inputs.
16 VDD power_in Positive supply; recommended VDD-VSS is 3 V to 15 V and the absolute maximum VDD-VSS is 18 V.

Key specifications

Parameter Value
Manufacturer MSKSEMI
Package SOP-16
Category Interface
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC supply voltage (VDD-VSS), absolute maximum VDD-VSS -0.5 18 V 3
Analog supply voltage (VDD-VEE), absolute maximum VDD-VEE 18 V 3
DC input voltage (absolute maximum) VIN -0.5 V Printed as -0.5+VSS ~ VDD+0.5 V; the upper limit is relative to VDD, not a fixed number 3
Power dissipation, absolute maximum PD 500 mW 3
Operating temperature, absolute maximum TA -40 85 ℃ 3
Storage temperature, absolute maximum TS -65 150 ℃ 3
Lead soldering temperature, absolute maximum TW 260 ℃ 10 s 3
DC supply voltage (VDD-VSS), recommended VDD-VSS 3 15 V 4
Control input voltage, recommended VIS 0 V Maximum printed as VDD-VSS 4
Analog supply voltage (VDD-VEE), recommended VDD-VEE 0 15 V 4
Analog input/output voltage, recommended VIN, VOUT 0 V Maximum printed as VDD-VEE 4
Operating temperature, recommended TA -40 85 ℃ 4
High-level input voltage VIH 3.5 V VDD=5 V; VIH=VDD through 1k; VEE=VSS; RL=1kΩ to VSS; IIS<2uA on all OFF channels 4
High-level input voltage VIH 7 V VDD=10 V; VIH=VDD through 1k; VEE=VSS; RL=1kΩ to VSS; IIS<2uA on all OFF channels 4
High-level input voltage VIH 11 V VDD=15 V; VIH=VDD through 1k; VEE=VSS; RL=1kΩ to VSS; IIS<2uA on all OFF channels 4
Low-level input voltage VIL 1.5 V VDD=5 V; VIL=VDD through 1k 4
Low-level input voltage VIL 3 V VDD=10 V; VIL=VDD through 1k 4
Low-level input voltage VIL 4 V VDD=15 V; VIL=VDD through 1k 4
On-resistance RON 180 Ω VDD=5 V; 0≤VIS≤VDD 4
On-resistance RON 115 Ω VDD=10 V; 0≤VIS≤VDD 4
On-resistance RON 90 Ω VDD=15 V; 0≤VIS≤VDD 4
On-resistance difference between adjacent channels △RON 15 Ω VDD=5 V 4
On-resistance difference between adjacent channels △RON 10 Ω VDD=10 V 4
On-resistance difference between adjacent channels △RON 5 Ω VDD=15 V 4
Off-channel leakage current IOFF -100 100 nA Input/output channels OFF, INH=VDD; VDD=18 V 4
Input current IIN -0.1 0.01 0.1 uA VIN=VDD or VSS; VDD=18 V 4
Quiescent supply current IDD 0.01 5 uA VIN=VDD or VSS; VDD=5 V 4
Quiescent supply current IDD 0.01 10 uA VIN=VDD or VSS; VDD=10 V 4
Quiescent supply current IDD 0.01 20 uA VIN=VDD or VSS; VDD=15 V 4
Propagation delay, signal input to output tpd 15 ns VDD=5 V; VIS=VDD, RL=200k, CL=50pF 4
Propagation delay, signal input to output tpd 10 ns VDD=10 V; VIS=VDD, RL=200k, CL=50pF 4
Propagation delay, signal input to output tpd 7 ns VDD=15 V; VIS=VDD, RL=200k, CL=50pF 4
Propagation delay, address to signal output tpd 100 ns VDD=5 V; CL=50pF, RL=10k; channels ON or OFF 4
Propagation delay, address to signal output tpd 80 ns VDD=10 V; CL=50pF, RL=10k; channels ON or OFF 4
Propagation delay, address to signal output tpd 50 ns VDD=15 V; CL=50pF, RL=10k; channels ON or OFF 4
Propagation delay, inhibit to signal output (channel turning ON) tpd 100 ns VDD=5 V; CL=50pF, RL=1k 5
Propagation delay, inhibit to signal output (channel turning ON) tpd 50 ns VDD=10 V; CL=50pF, RL=1k 5
Propagation delay, inhibit to signal output (channel turning ON) tpd 30 ns VDD=15 V; CL=50pF, RL=1k 5
Propagation delay, inhibit to signal output (channel turning OFF) tpd 100 ns VDD=5 V; CL=50pF, RL=10k 5
Propagation delay, inhibit to signal output (channel turning OFF) tpd 50 ns VDD=10 V; CL=50pF, RL=10k 5
Propagation delay, inhibit to signal output (channel turning OFF) tpd 30 ns VDD=15 V; CL=50pF, RL=10k 5

CAD (KiCad official)

  • Symbol: CD4053BM-MS
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4053bm-ms-etched.step / cd4053bm-ms-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4053bm-ms.step / cd4053bm-ms.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MSKSEMI datasheet (9 pp, sha256 77edea487671c17d, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF