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CD4053BE

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Texas Instruments Analog Switches, Multiplexers, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4053BE

Texas Instruments · Analog Switches, Multiplexers · PDIP-16

CD4053BE from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BY bidirectional Channel B, Y-side input/output; analog signal path to common pin 15 (BX or BY), and analog signals may swing from VEE to VDD.
2 BX bidirectional Channel B, X-side input/output; analog signal path to common pin 15 (BX or BY), and analog signals may swing from VEE to VDD.
3 CY bidirectional Channel C, Y-side input/output; analog signal path to common pin 4 (CX or CY), and analog signals may swing from VEE to VDD.
4 CX or CY bidirectional Common C output/input; connects to CX or CY as selected by the channel-select inputs per Table 7-1, and analog signals may swing from VEE to VDD.
5 CX bidirectional Channel C, X-side input/output; analog signal path to common pin 4 (CX or CY), and analog signals may swing from VEE to VDD.
6 INH input Inhibit input that disables all channels when high (logic 1 = VDD, logic 0 = VSS), per Table 7-1.
7 VEE power_in Negative power supply input; dual-supply operation is specified from ±3 V to ±10 V, and analog signals may swing down to VEE.
8 VSS power_in Ground reference for the digital control inputs (logic 0 = VSS); all voltages are referenced to VSS, with the supply limited to -0.5 V to 20 V referenced to VSS.
9 C input Channel-select input C that selects the active channel per Table 7-1 (logic 0 = VSS, logic 1 = VDD).
10 B input Channel-select input B that selects the active channel per Table 7-1 (logic 0 = VSS, logic 1 = VDD).
11 A input Channel-select input A that selects the active channel per Table 7-1 (logic 0 = VSS, logic 1 = VDD).
12 AX bidirectional Channel A, X-side input/output; analog signal path to common pin 14 (AX or AY), and analog signals may swing from VEE to VDD.
13 AY bidirectional Channel A, Y-side input/output; analog signal path to common pin 14 (AX or AY), and analog signals may swing from VEE to VDD.
14 AX or AY bidirectional Common A output/input; connects to AX or AY as selected by the channel-select inputs per Table 7-1, and analog signals may swing from VEE to VDD.
15 BX or BY bidirectional Common B output/input; connects to BX or BY as selected by the channel-select inputs per Table 7-1, and analog signals may swing from VEE to VDD.
16 VDD power_in Positive power supply input; single-supply range is 3 V to 20 V (performance degrades below 3 V), with the supply limited to 20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Interface
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (V+ to V-) -0.5 20 V Voltage referenced to VSS terminal 5
DC input voltage -0.5 V Upper limit printed as VDD+0.5 5
DC input current, any one input -10 10 mA Any one input 5
Maximum junction temperature, plastic package TJMAX2 150 °C Plastic package 5
Storage temperature Tstg -65 150 °C 5
ESD human body model (HBM), all pins V(ESD) -3000 3000 V Per ANSI/ESDA/JEDEC JS-001 5
ESD charged device model (CDM), all pins V(ESD) -2000 2000 V Per JEDEC JESD22-C101 5
Operating temperature range -55 125 °C Natural ventilation 5
Junction-to-ambient thermal resistance, E (PDIP) 16-pin RθJA 67 °C/W E (PDIP) 16-pin package 5
Static device current IDD 60 µA VEE=0V, VSS=0V, VDD=5V; -55°C 6
Static device current IDD 17 60 µA VEE=0V, VSS=0V, VDD=5V; 25°C 6
Static device current IDD 150 µA VEE=0V, VSS=0V, VDD=5V; 85°C 6
Static device current IDD 18 60 µA VEE=0V, VSS=0V, VDD=10V; 25°C 6
Static device current IDD 300 µA VEE=0V, VSS=0V, VDD=10V; 85°C 6
Static device current IDD 600 µA VEE=0V, VSS=0V, VDD=15V; 85°C 6
Static device current IDD 100 µA VEE=0V, VSS=0V, VDD=20V; -55°C 6
Static device current IDD 18 100 µA VEE=0V, VSS=0V, VDD=20V; 25°C 6
Static device current IDD 3000 µA VEE=0V, VSS=0V, VDD=20V; 85°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 800 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=5V; -55°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 850 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=5V; -40°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 470 1050 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=5V; 25°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 1200 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=5V; 85°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 1300 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=5V; 125°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 310 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=10V; -55°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 300 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=10V; -40°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 180 400 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=10V; 25°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 520 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=10V; 85°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 550 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=10V; 125°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 200 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=15V; -55°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 210 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=15V; -40°C 6
On-resistance, drain-source (0 ≤ VIS ≤ VDD) rON 125 240 Ω 0 ≤ VIS ≤ VDD; VEE=0V, VSS=0V, VDD=15V; 25°C 6
Off-channel leakage current (any channel off, or all channels off common) -100 100 nA VEE=0V, VSS=0V, VDD=18V; -55°C 7
Off-channel leakage current (any channel off, or all channels off common) -100 0.3 100 nA VEE=0V, VSS=0V, VDD=18V; 25°C 7
Off-channel leakage current (any channel off, or all channels off common) -1000 1000 nA VEE=0V, VSS=0V, VDD=18V; 85°C 7
Input low voltage (control/address/inhibit) VIL 0.8 V VDD=5V; 25°C 7
Input high voltage (control/address/inhibit) VIH 3.5 V VDD=5V; 25°C 8
Input high voltage (control/address/inhibit) VIH 7 V VDD=10V; 25°C 8
Input high voltage (control/address/inhibit) VIH 11 V VDD=15V; 25°C 8
Input current IIN -1 0.6 1 µA VIN = 0, 18; 18V; 25°C 8
Input capacitance (any address or inhibit input) CIN 5 7.5 pF VEE=-5V, VSS=0V, VDD=5V; 25°C 8
Propagation delay, address to signal output (channel on or off) 450 720 ns VEE=0V, VSS=0V, VDD=5V; tr,tf=20ns, CL=50pF, RL=10kΩ 8
Propagation delay 30 60 ns VDD=5V; 25°C; RL=200kΩ, CL=50pF, tr,tf=20ns 7

CAD (KiCad official)

  • Symbol: CD4053BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4053be-etched.step / cd4053be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4053be.step / cd4053be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 18e0ea9acf5c1eb5, retrieved 2026-10-16, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF