# CD4053BDRG

**HANSCHIP semiconductor** · Analog Switches, Multiplexers · SOP-16

CD4053BDRG from HANSCHIP semiconductor, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1B | bidirectional | Independent input/output of switch B, connected to ZB when SB is high and the enable input is low. |
| 2 | Y0B | bidirectional | Independent input/output of switch B, connected to ZB when SB is low and the enable input is low. |
| 3 | Y1C | bidirectional | Independent input/output of switch C, connected to ZC when SC is high and the enable input is low. |
| 4 | ZC | bidirectional | Common input/output of switch C, which can swing between VEE and VDD. |
| 5 | Y0C | bidirectional | Independent input/output of switch C, connected to ZC when SC is low and the enable input is low. |
| 6 | E | input | Active-low enable input; low enables the selected switches and high puts all switches in the high-impedance off state regardless of SA to SC. |
| 7 | VEE | power_in | Negative supply voltage for the analog switches, with VDD-VEE recommended 5.0 V to 15 V and VEE from -6.0 V to 0 V; tied to VSS for digital multiplexing. |
| 8 | VSS | power_in | Ground pin, the supply reference for the digital control inputs SA to SC and enable. |
| 9 | SC | input | Select input for switch C, selecting Y0C when low and Y1C when high. |
| 10 | SB | input | Select input for switch B, selecting Y0B when low and Y1B when high. |
| 11 | SA | input | Select input for switch A, selecting Y0A when low and Y1A when high. |
| 12 | Y0A | bidirectional | Independent input/output of switch A, connected to ZA when SA is low and the enable input is low. |
| 13 | Y1A | bidirectional | Independent input/output of switch A, connected to ZA when SA is high and the enable input is low. |
| 14 | ZA | bidirectional | Common input/output of switch A, which can swing between VEE and VDD. |
| 15 | ZB | bidirectional | Common input/output of switch B, which can swing between VEE and VDD. |
| 16 | VDD | power_in | Positive supply voltage, with VDD-VSS range of 3 to 18 V and absolute maximum +18 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | SOP-16 |
| Category | Interface |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| On-resistance (Vis=0~VDD-VEE) | RON |  | 350 | 2500 | Ω | VDD-VEE=5V; Vis=0～VDD－VEE; see Fig.1 | 6 |
| On-resistance (Vis=0~VDD-VEE) | RON |  | 80 | 245 | Ω | VDD-VEE=9V; Vis=0～VDD－VEE; see Fig.1 | 6 |
| On-resistance (Vis=0) | RON |  | 115 | 340 | Ω | VDD-VEE=5V; Vis=0; see Fig.1 | 6 |
| On-resistance (Vis=0) | RON |  | 50 | 160 | Ω | VDD-VEE=9V; Vis=0; see Fig.1 | 6 |
| On-resistance (Vis=VDD-VEE) | RON |  | 120 | 365 | Ω | VDD-VEE=5V; Vis=VDD－VEE; see Fig.1 | 6 |
| On-resistance (Vis=VDD-VEE) | RON |  | 65 | 200 | Ω | VDD-VEE=9V; Vis=VDD－VEE; see Fig.1 | 6 |
| Off-state leakage current (all channels off) | IOZZ |  |  | 1000 | nΑ | VDD-VEE=9V; all channels off, at VDD | 6 |
| Off-state leakage current (any channel off) | IOZY |  |  | 200 | nΑ | VDD-VEE=9V; any channel off, at VEE | 6 |
| Supply voltage range | VDD | -0.5 |  | 18 | V |  | 5 |
| Supply voltage range (VDD-VEE) | VDD- VEE | -0.5 |  | 18 | V |  | 5 |
| Input voltage range | VI | -0.5 |  |  | V |  | 5 |
| Static current | IQ |  |  | 2 | μA | VDD-VEE=12V | 5 |
| High-level input current | /IIH/ |  |  | 1 | μA | VDD=5V, VI=VDD | 5 |
| Low-level input current | /IIL/ |  |  | 1 | μA | VDD=5V, VI=0V | 5 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI<-0.5V or VI>VDD+0.5V | 5 |
| Input/output clamp current | IIOK | -20 |  | 20 | mA | VIO<VEE-0.5V or VIO>VDD+0.5V | 5 |
| Switch on-state current | IT | -25 |  | 25 | mA | VO=-0.5V～VDD+0.5V | 5 |
| VDD or GND current | IDD, IGND | -50 |  | 50 | mA |  | 5 |
| Power dissipation | PD |  |  | 500 | mW |  | 5 |
| Storage temperature | TSTG | -65 |  | 150 | ℃ |  | 5 |
| Operating temperature (absolute maximum) | TOP | -40 |  | 85 | ℃ |  | 5 |
| Soldering temperature | TL |  |  | 245 | ℃ | 10 s; SOP package | 5 |
| Supply voltage | VDD | 3 | 5 | 18 | V |  | 6 |
| Supply voltage | VEE | -6 |  | 0 | V |  | 6 |
| Supply voltage (VDD-VEE) | VDD- VEE | 5 |  | 15 | V |  | 6 |
| Input voltage | VI | 0 |  |  | V |  | 6 |
| Input rise/fall time | tr,tf |  |  | 1000 | ns | VCC=3.0V | 6 |
| Input rise/fall time | tr,tf |  |  | 500 | ns | VCC=5.0V | 6 |
| Input rise/fall time | tr,tf |  |  | 400 | ns | VCC=6.0V | 6 |
| Operating temperature | TOP | -40 |  | 85 | ℃ |  | 6 |
| Propagation delay Vis to Vos, high to low | tPHL |  | 10 | 20 | ns | VDD=5V; Vis→Vos; note 1; Tamb=25℃, VSS=VEE=0V | 8 |
| Propagation delay Vis to Vos, high to low | tPHL |  | 5 | 10 | ns | VDD=9V; Vis→Vos; note 1; Tamb=25℃, VSS=VEE=0V | 8 |
| Propagation delay Vis to Vos, low to high | tPLH |  | 15 | 30 | ns | VDD=5V; Vis→Vos; note 1; Tamb=25℃, VSS=VEE=0V | 8 |
| Propagation delay Vis to Vos, low to high | tPLH |  | 5 | 10 | ns | VDD=9V; Vis→Vos; note 1; Tamb=25℃, VSS=VEE=0V | 8 |
| Propagation delay Sn to Vos, high to low | tPHL |  | 200 | 400 | ns | VDD=5V; Sn→Vos; note 2 | 8 |
| Propagation delay Sn to Vos, high to low | tPHL |  | 85 | 170 | ns | VDD=9V; Sn→Vos; note 2 | 8 |
| Propagation delay Sn to Vos, low to high | tPLH |  | 275 | 555 | ns | VDD=5V; Sn→Vos; note 2 | 8 |
| Propagation delay Sn to Vos, low to high | tPLH |  | 100 | 200 | ns | VDD=9V; Sn→Vos; note 2 | 8 |
| Output disable time to Vos, high | tPHZ |  | 200 | 400 | ns | VDD=5V; enable→Vos high; note 3 | 8 |
| Output disable time to Vos, high | tPHZ |  | 115 | 230 | ns | VDD=9V; enable→Vos high; note 3 | 8 |
| Output disable time to Vos, low | tPLZ |  | 200 | 400 | ns | VDD=5V; enable→Vos low; note 3 | 8 |
| Output disable time to Vos, low | tPLZ |  | 120 | 245 | ns | VDD=9V; enable→Vos low; note 3 | 8 |
| Output enable time to Vos, high | tPZH |  | 260 | 525 | ns | VDD=5V; enable→Vos high; note 3 | 8 |
| Output enable time to Vos, high | tPZH |  | 95 | 190 | ns | VDD=9V; enable→Vos high; note 3 | 8 |
| Output enable time to Vos, low | tPZL |  | 280 | 565 | ns | VDD=5V; enable→Vos low; note 3 | 8 |
| Output enable time to Vos, low | tPZL |  | 105 | 205 | ns | VDD=9V; enable→Vos low; note 3 | 8 |
| Crosstalk, enable or select to output |  |  |  | 50 | mV | VDD=5V and 9V; enable or Sn to output; note 6 | 8 |

## CAD (KiCad official)

- Symbol: `CD4053BDRG`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `cd4053bdrg-etched.step` / `cd4053bdrg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4053bdrg.step` / `cd4053bdrg.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HANSCHIP semiconductor datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586209370060804096) (13 pp, sha256 `7dfc7713eb0f3a08`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4053bdrg-datasheet.pdf)