main
Download ZIP Propose a change
Made with kicad-footprint-generator 10.0 · KiCad file format 20260206
Name Last commit message Last updated
docs cd4053b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers cross-highlight symbol + footprint viewers · Ray 2mo ago
cd4053b-etched.fit.json cd4053b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4053b-etched.glb cd4053b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4053b-etched.step cd4053b: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
CD4053B.adom-lbr.json CD4053B: validated Fusion/EAGLE library + adom-lbr hub, generated from this page's KiCad sources · Ray 2mo ago
cd4053b.glb Publish 0.1.0 · Ray 2mo ago
cd4053b.kicad_mod Publish 0.1.0 · Ray 2mo ago
cd4053b.kicad_sym Publish 0.1.0 · Ray 2mo ago
cd4053b.lbr add validated EAGLE .lbr (Fusion library) · Ray 2mo ago
CD4053B.lbr CD4053B: validated Fusion/EAGLE library + adom-lbr hub, generated from this page's KiCad sources · Ray 2mo ago
cd4053b.step add .step (Fusion 3D source) · Ray 2mo ago
package.json Publish 0.1.0 · Ray 2mo ago
page.json cd4053b: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md cd4053b: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

CD4053B

Texas Instruments · Triple 2-channel analog mux / demux · SOIC-16

Three independent single-pole double-throw analog switches in a SOIC-16, part of the CD4051/4052/4053 mux family. Each of the three switches (A, B, C) has its own select input that connects its common pin to one of two channels, bidirectionally, so it works as three 2-to-1 muxes or 1-to-2 demuxes. A shared inhibit (INH) opens all switches, and a separate VEE lets it pass bipolar analog signals below ground. Use it to swap between two signal sources per channel, route stereo audio, or steer references. Runs 3-18 V (VDD).

Pinout

Pin Name Type Function
1 BY bidirectional B-switch Y-channel in/out (analog). Connects to common BX-OR-BY (pin 15) when address B selects the Y side and INH is low.
2 BX bidirectional B-switch X-channel in/out (analog). Connects to common BX-OR-BY (pin 15) when address B selects the X side and INH is low.
3 CY bidirectional C-switch Y-channel in/out (analog). Connects to common CX-OR-CY (pin 4) when address C selects the Y side and INH is low.
4 CX_OR_CY bidirectional C-switch common out/in (analog). Multiplexed pole of the C SPDT: routes to CX (pin 5) or CY (pin 3) per address bit C when INH is low.
5 CX bidirectional C-switch X-channel in/out (analog). Connects to common CX-OR-CY (pin 4) when address C selects the X side and INH is low.
6 INH input Inhibit (active high, digital). When INH = 1 all three analog switches are turned OFF (all channels disabled). Digital input level: 3-20 V referenced to VSS; see Table 7-1.
7 VEE power_in Negative analog supply. Sets the lower bound of the analog signal range; may be equal to VSS for single-supply operation or below VSS for a dual analog supply (VDD − VEE ≤ 20 V absolute max).
8 VSS power_in Ground / digital-logic negative supply reference. Reference for the digital control inputs (A, B, C, INH). Typically 0 V.
9 C input Digital channel-select C: selects X (0) or Y (1) side of the C analog switch. Referenced VSS to VDD (3-20 V logic level). See Table 7-1.
10 B input Digital channel-select B: selects X (0) or Y (1) side of the B analog switch. Referenced VSS to VDD (3-20 V logic level). See Table 7-1.
11 A input Digital channel-select A: selects X (0) or Y (1) side of the A analog switch. Referenced VSS to VDD (3-20 V logic level). See Table 7-1.
12 AX bidirectional A-switch X-channel in/out (analog). Connects to common AX-OR-AY (pin 14) when address A selects the X side and INH is low.
13 AY bidirectional A-switch Y-channel in/out (analog). Connects to common AX-OR-AY (pin 14) when address A selects the Y side and INH is low.
14 AX_OR_AY bidirectional A-switch common out/in (analog). Multiplexed pole of the A SPDT: routes to AX (pin 12) or AY (pin 13) per address bit A when INH is low.
15 BX_OR_BY bidirectional B-switch common out/in (analog). Multiplexed pole of the B SPDT: routes to BX (pin 2) or BY (pin 1) per address bit B when INH is low.
16 VDD power_in Positive supply. Digital logic supply and upper bound of the analog signal range. Operating range 3-20 V (performance degrades below 3 V); VDD − VEE ≤ 20 V absolute max.

Key specifications

Parameter Value
Type Triple 2-channel analog mux/demux
Switches 3 independent SPDT (bidirectional)
Control one select per switch (A/B/C) + INH
Signal range bipolar (VDD to VEE)
Supply (VDD) 3-18 V
On-resistance ~125 Ω typ at 15 V
Family CD4051/4052/4053
Package SOIC-16

Ordering variants

Same part, different packaging or reel option.

  • CD4053BM (SOIC-16, tube)
  • CD4053BM96 (SOIC-16, tape & reel)

CAD (KiCad official)

  • Symbol: 4xxx:4053
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D)
  • 3D model files: cd4053b-etched.step / cd4053b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4053b.step / cd4053b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 3fbac7b3f3463b15, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF