component
CD4052S
Public Made by Adomby adom
GR Analog Switches, Multiplexers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD4052S
GR · Analog Switches, Multiplexers · SOP-16
CD4052S from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y0 | passive | Y0 analog channel terminal, connected to COMY when A=0, B=0 and INH=0 per the truth table. |
| 2 | Y2 | passive | Y2 analog channel terminal, connected to COMY when A=0, B=1 and INH=0 per the truth table. |
| 3 | COMY | passive | Common analog terminal for the Y side, switched to whichever of Y0-Y3 is selected by A, B and INH. |
| 4 | Y3 | passive | Y3 analog channel terminal, connected to COMY when A=1, B=1 and INH=0 per the truth table. |
| 5 | Y1 | passive | Y1 analog channel terminal, connected to COMY when A=1, B=0 and INH=0 per the truth table. |
| 6 | INH | input | Inhibit (enable control) input; when high all channels are turned off, and when low the channel selected by A and B is on. |
| 7 | VEE | power_in | Negative supply for the analog switches; recommended VDD-VEE range 0 to 15 V with an absolute maximum of 18 V. |
| 8 | VSS | power_in | Power ground and reference for the control inputs; recommended VDD-VSS range is 3 to 15 V. |
| 9 | B | input | Binary channel-select address input B, used together with A to select one of four channels per the truth table. |
| 10 | A | input | Binary channel-select address input A, used together with B to select one of four channels per the truth table. |
| 11 | X3 | passive | X3 analog channel terminal, connected to COMX when A=1, B=1 and INH=0 per the truth table. |
| 12 | X0 | passive | X0 analog channel terminal, connected to COMX when A=0, B=0 and INH=0 per the truth table. |
| 13 | COMX | passive | Common analog terminal for the X side, switched to whichever of X0-X3 is selected by A, B and INH. |
| 14 | X1 | passive | X1 analog channel terminal, connected to COMX when A=1, B=0 and INH=0 per the truth table. |
| 15 | X2 | passive | X2 analog channel terminal, connected to COMX when A=0, B=1 and INH=0 per the truth table. |
| 16 | VDD | power_in | Positive supply; recommended VDD-VSS range is 3 to 15 V with an absolute maximum of 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage (直流电源电压) | VDD-VSS | -0.5 | 18 | V | 2 | ||
| Analog supply voltage (模拟电源电压) | VDD-VEE | 18 | V | 2 | |||
| Power dissipation (功耗) | PD | 500 | mW | 2 | |||
| Operating temperature (工作温度) | TA | 0 | 70 | ℃ | 2 | ||
| Storage temperature (存储温度) | TS | -65 | 150 | ℃ | 2 | ||
| Lead soldering temperature (引脚焊接温度) | TW | 260 | ℃ | 10 s | 2 | ||
| DC supply voltage (直流电源电压) | VDD-VSS | 3 | 15 | V | 3 | ||
| Control input voltage (控制输入电压) | VIS | 0 | V | 3 | |||
| Analog supply voltage (模拟电源电压) | VDD-VEE | 0 | 15 | V | 3 | ||
| Analog input/output voltage (模拟输入输出电压) | VIN, VOUT | 0 | V | 3 | |||
| Operating temperature (工作温度) | TA | 0 | 60 | ℃ | 3 | ||
| High-level input voltage (高电平有效输入电压) | VIH | 3.5 | V | VIH=VDD through 1k, VEE=VSS, RL=1kΩ to VSS, IIS<2uA on all OFF channels; VDD=5V | 3 | ||
| High-level input voltage (高电平有效输入电压) | VIH | 7 | V | VIH=VDD through 1k, VEE=VSS, RL=1kΩ to VSS, IIS<2uA on all OFF channels; VDD=10V | 3 | ||
| High-level input voltage (高电平有效输入电压) | VIH | 11 | V | VIH=VDD through 1k, VEE=VSS, RL=1kΩ to VSS, IIS<2uA on all OFF channels; VDD=15V | 3 | ||
| Low-level input voltage (低电平有效输入电压) | VIL | 1.5 | V | VIL=VDD through 1k; VDD=5V | 3 | ||
| Low-level input voltage (低电平有效输入电压) | VIL | 3 | V | VIL=VDD through 1k; VDD=10V | 3 | ||
| Low-level input voltage (低电平有效输入电压) | VIL | 4 | V | VIL=VDD through 1k; VDD=15V | 3 | ||
| Channel leakage current (漏电流) | IOFF | -100 | 100 | nA | Input/output channels OFF, INH=VDD; VDD=18V | 3 | |
| Input current (输入电流) | IIN | -0.1 | 0.01 | 0.1 | uA | VIN=VDD or VSS; VDD=18V | 3 |
| Quiescent current (静态电流) | IDD | 0.01 | 5 | uA | VIN=VDD or VSS; VDD=5V | 3 | |
| Quiescent current (静态电流) | IDD | 0.01 | 10 | uA | VIN=VDD or VSS; VDD=10V | 3 | |
| Quiescent current (静态电流) | IDD | 0.01 | 20 | uA | VIN=VDD or VSS; VDD=15V | 3 | |
| On-resistance (导通电阻) | RON | 155 | Ω | 0≤VIS≤VDD; VDD=5V | 3 | ||
| On-resistance (导通电阻) | RON | 85 | Ω | 0≤VIS≤VDD; VDD=10V | 3 | ||
| On-resistance (导通电阻) | RON | 60 | Ω | 0≤VIS≤VDD; VDD=15V | 3 | ||
| On-resistance difference between adjacent channels (相邻通道导通电阻差) | △RON | 15 | Ω | VDD=5V | 3 | ||
| On-resistance difference between adjacent channels (相邻通道导通电阻差) | △RON | 10 | Ω | VDD=10V | 3 | ||
| On-resistance difference between adjacent channels (相邻通道导通电阻差) | △RON | 5 | Ω | VDD=15V | 3 | ||
| Input capacitance (输入电容) | CIN | 7.5 | pF | Any input; VDD=5V | 3 | ||
| Channel input capacitance (通道输入电容) | CIS | 5 | pF | 3 | |||
| Output capacitance (输出电容) | COS | 9 | pF | 3 | |||
| On-channel capacitance (导通电容) | CIOS | 0.2 | pF | 3 | |||
| Propagation delay, signal input to output (传输延迟时间 Signal Input to Output) | tpd | 15 | ns | VIS=VDD, RL=200kΩ, CL=50pF; VDD=5V; VSS=VEE, Ta=25℃, tr=tf=20ns | 3 | ||
| Propagation delay, signal input to output (传输延迟时间 Signal Input to Output) | tpd | 10 | ns | VIS=VDD, RL=200kΩ, CL=50pF; VDD=10V; VSS=VEE, Ta=25℃, tr=tf=20ns | 3 | ||
| Propagation delay, signal input to output (传输延迟时间 Signal Input to Output) | tpd | 7 | ns | VIS=VDD, RL=200kΩ, CL=50pF; VDD=15V; VSS=VEE, Ta=25℃, tr=tf=20ns | 3 | ||
| Propagation delay, address-to-signal OUT (传输延迟时间 Address-to-Signal OUT) | tpd | 100 | ns | CL=50pF, RL=10kΩ; VDD=5V; channels ON or OFF | 3 | ||
| Propagation delay, address-to-signal OUT (传输延迟时间 Address-to-Signal OUT) | tpd | 80 | ns | CL=50pF, RL=10kΩ; VDD=10V; channels ON or OFF | 3 | ||
| Propagation delay, address-to-signal OUT (传输延迟时间 Address-to-Signal OUT) | tpd | 50 | ns | CL=50pF, RL=10kΩ; VDD=15V; channels ON or OFF | 3 | ||
| Propagation delay, inhibit-to-signal OUT channel turning ON (传输延迟时间 Inhibit-to-Signal OUT) | tpd | 100 | ns | CL=50pF, RL=1kΩ; VDD=5V | 4 | ||
| Propagation delay, inhibit-to-signal OUT channel turning ON (传输延迟时间 Inhibit-to-Signal OUT) | tpd | 50 | ns | CL=50pF, RL=1kΩ; VDD=10V | 4 | ||
| Propagation delay, inhibit-to-signal OUT channel turning ON (传输延迟时间 Inhibit-to-Signal OUT) | tpd | 30 | ns | CL=50pF, RL=1kΩ; VDD=15V | 4 | ||
| Propagation delay, inhibit-to-signal OUT channel turning OFF (传输延迟时间 Inhibit-to-Signal OUT) | tpd | 100 | ns | CL=50pF, RL=10kΩ; VDD=5V | 4 | ||
| Propagation delay, inhibit-to-signal OUT channel turning OFF (传输延迟时间 Inhibit-to-Signal OUT) | tpd | 50 | ns | CL=50pF, RL=10kΩ; VDD=10V | 4 | ||
| Propagation delay, inhibit-to-signal OUT channel turning OFF (传输延迟时间 Inhibit-to-Signal OUT) | tpd | 30 | ns | CL=50pF, RL=10kΩ; VDD=15V | 4 |
CAD (KiCad official)
- Symbol:
CD4052S - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4052s-etched.step/cd4052s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4052s.step/cd4052s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (5 pp, sha256
fa78cbf3db8a5087, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4052S
**GR** · Analog Switches, Multiplexers · SOP-16
CD4052S from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y0 | passive | Y0 analog channel terminal, connected to COMY when A=0, B=0 and INH=0 per the truth table. |
| 2 | Y2 | passive | Y2 analog channel terminal, connected to COMY when A=0, B=1 and INH=0 per the truth table. |
| 3 | COMY | passive | Common analog terminal for the Y side, switched to whichever of Y0-Y3 is selected by A, B and INH. |
| 4 | Y3 | passive | Y3 analog channel terminal, connected to COMY when A=1, B=1 and INH=0 per the truth table. |
| 5 | Y1 | passive | Y1 analog channel terminal, connected to COMY when A=1, B=0 and INH=0 per the truth table. |
| 6 | INH | input | Inhibit (enable control) input; when high all channels are turned off, and when low the channel selected by A and B is on. |
| 7 | VEE | power_in | Negative supply for the analog switches; recommended VDD-VEE range 0 to 15 V with an absolute maximum of 18 V. |
| 8 | VSS | power_in | Power ground and reference for the control inputs; recommended VDD-VSS range is 3 to 15 V. |
| 9 | B | input | Binary channel-select address input B, used together with A to select one of four channels per the truth table. |
| 10 | A | input | Binary channel-select address input A, used together with B to select one of four channels per the truth table. |
| 11 | X3 | passive | X3 analog channel terminal, connected to COMX when A=1, B=1 and INH=0 per the truth table. |
| 12 | X0 | passive | X0 analog channel terminal, connected to COMX when A=0, B=0 and INH=0 per the truth table. |
| 13 | COMX | passive | Common analog terminal for the X side, switched to whichever of X0-X3 is selected by A, B and INH. |
| 14 | X1 | passive | X1 analog channel terminal, connected to COMX when A=1, B=0 and INH=0 per the truth table. |
| 15 | X2 | passive | X2 analog channel terminal, connected to COMX when A=0, B=1 and INH=0 per the truth table. |
| 16 | VDD | power_in | Positive supply; recommended VDD-VSS range is 3 to 15 V with an absolute maximum of 18 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-16 |
| Category | Interface |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage (直流电源电压) | VDD-VSS | -0.5 | | 18 | V | | 2 |
| Analog supply voltage (模拟电源电压) | VDD-VEE | | | 18 | V | | 2 |
| Power dissipation (功耗) | PD | | | 500 | mW | | 2 |
| Operating temperature (工作温度) | TA | 0 | | 70 | ℃ | | 2 |
| Storage temperature (存储温度) | TS | -65 | | 150 | ℃ | | 2 |
| Lead soldering temperature (引脚焊接温度) | TW | | | 260 | ℃ | 10 s | 2 |
| DC supply voltage (直流电源电压) | VDD-VSS | 3 | | 15 | V | | 3 |
| Control input voltage (控制输入电压) | VIS | 0 | | | V | | 3 |
| Analog supply voltage (模拟电源电压) | VDD-VEE | 0 | | 15 | V | | 3 |
| Analog input/output voltage (模拟输入输出电压) | VIN, VOUT | 0 | | | V | | 3 |
| Operating temperature (工作温度) | TA | 0 | | 60 | ℃ | | 3 |
| High-level input voltage (高电平有效输入电压) | VIH | 3.5 | | | V | VIH=VDD through 1k, VEE=VSS, RL=1kΩ to VSS, IIS<2uA on all OFF channels; VDD=5V | 3 |
| High-level input voltage (高电平有效输入电压) | VIH | 7 | | | V | VIH=VDD through 1k, VEE=VSS, RL=1kΩ to VSS, IIS<2uA on all OFF channels; VDD=10V | 3 |
| High-level input voltage (高电平有效输入电压) | VIH | 11 | | | V | VIH=VDD through 1k, VEE=VSS, RL=1kΩ to VSS, IIS<2uA on all OFF channels; VDD=15V | 3 |
| Low-level input voltage (低电平有效输入电压) | VIL | | | 1.5 | V | VIL=VDD through 1k; VDD=5V | 3 |
| Low-level input voltage (低电平有效输入电压) | VIL | | | 3 | V | VIL=VDD through 1k; VDD=10V | 3 |
| Low-level input voltage (低电平有效输入电压) | VIL | | | 4 | V | VIL=VDD through 1k; VDD=15V | 3 |
| Channel leakage current (漏电流) | IOFF | -100 | | 100 | nA | Input/output channels OFF, INH=VDD; VDD=18V | 3 |
| Input current (输入电流) | IIN | -0.1 | 0.01 | 0.1 | uA | VIN=VDD or VSS; VDD=18V | 3 |
| Quiescent current (静态电流) | IDD | | 0.01 | 5 | uA | VIN=VDD or VSS; VDD=5V | 3 |
| Quiescent current (静态电流) | IDD | | 0.01 | 10 | uA | VIN=VDD or VSS; VDD=10V | 3 |
| Quiescent current (静态电流) | IDD | | 0.01 | 20 | uA | VIN=VDD or VSS; VDD=15V | 3 |
| On-resistance (导通电阻) | RON | | 155 | | Ω | 0≤VIS≤VDD; VDD=5V | 3 |
| On-resistance (导通电阻) | RON | | 85 | | Ω | 0≤VIS≤VDD; VDD=10V | 3 |
| On-resistance (导通电阻) | RON | | 60 | | Ω | 0≤VIS≤VDD; VDD=15V | 3 |
| On-resistance difference between adjacent channels (相邻通道导通电阻差) | △RON | | 15 | | Ω | VDD=5V | 3 |
| On-resistance difference between adjacent channels (相邻通道导通电阻差) | △RON | | 10 | | Ω | VDD=10V | 3 |
| On-resistance difference between adjacent channels (相邻通道导通电阻差) | △RON | | 5 | | Ω | VDD=15V | 3 |
| Input capacitance (输入电容) | CIN | | 7.5 | | pF | Any input; VDD=5V | 3 |
| Channel input capacitance (通道输入电容) | CIS | | 5 | | pF | | 3 |
| Output capacitance (输出电容) | COS | | 9 | | pF | | 3 |
| On-channel capacitance (导通电容) | CIOS | | 0.2 | | pF | | 3 |
| Propagation delay, signal input to output (传输延迟时间 Signal Input to Output) | tpd | | 15 | | ns | VIS=VDD, RL=200kΩ, CL=50pF; VDD=5V; VSS=VEE, Ta=25℃, tr=tf=20ns | 3 |
| Propagation delay, signal input to output (传输延迟时间 Signal Input to Output) | tpd | | 10 | | ns | VIS=VDD, RL=200kΩ, CL=50pF; VDD=10V; VSS=VEE, Ta=25℃, tr=tf=20ns | 3 |
| Propagation delay, signal input to output (传输延迟时间 Signal Input to Output) | tpd | | 7 | | ns | VIS=VDD, RL=200kΩ, CL=50pF; VDD=15V; VSS=VEE, Ta=25℃, tr=tf=20ns | 3 |
| Propagation delay, address-to-signal OUT (传输延迟时间 Address-to-Signal OUT) | tpd | | 100 | | ns | CL=50pF, RL=10kΩ; VDD=5V; channels ON or OFF | 3 |
| Propagation delay, address-to-signal OUT (传输延迟时间 Address-to-Signal OUT) | tpd | | 80 | | ns | CL=50pF, RL=10kΩ; VDD=10V; channels ON or OFF | 3 |
| Propagation delay, address-to-signal OUT (传输延迟时间 Address-to-Signal OUT) | tpd | | 50 | | ns | CL=50pF, RL=10kΩ; VDD=15V; channels ON or OFF | 3 |
| Propagation delay, inhibit-to-signal OUT channel turning ON (传输延迟时间 Inhibit-to-Signal OUT) | tpd | | 100 | | ns | CL=50pF, RL=1kΩ; VDD=5V | 4 |
| Propagation delay, inhibit-to-signal OUT channel turning ON (传输延迟时间 Inhibit-to-Signal OUT) | tpd | | 50 | | ns | CL=50pF, RL=1kΩ; VDD=10V | 4 |
| Propagation delay, inhibit-to-signal OUT channel turning ON (传输延迟时间 Inhibit-to-Signal OUT) | tpd | | 30 | | ns | CL=50pF, RL=1kΩ; VDD=15V | 4 |
| Propagation delay, inhibit-to-signal OUT channel turning OFF (传输延迟时间 Inhibit-to-Signal OUT) | tpd | | 100 | | ns | CL=50pF, RL=10kΩ; VDD=5V | 4 |
| Propagation delay, inhibit-to-signal OUT channel turning OFF (传输延迟时间 Inhibit-to-Signal OUT) | tpd | | 50 | | ns | CL=50pF, RL=10kΩ; VDD=10V | 4 |
| Propagation delay, inhibit-to-signal OUT channel turning OFF (传输延迟时间 Inhibit-to-Signal OUT) | tpd | | 30 | | ns | CL=50pF, RL=10kΩ; VDD=15V | 4 |
## CAD (KiCad official)
- Symbol: `CD4052S`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `cd4052s-etched.step` / `cd4052s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4052s.step` / `cd4052s.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [GR datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8597542362684280832) (5 pp, sha256 `fa78cbf3db8a5087`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4052s-datasheet.pdf)