# CD4052BPWRG

**HANSCHIP semiconductor** · Analog Switches, Multiplexers · TSSOP-16

CD4052BPWRG from HANSCHIP semiconductor, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y0B | passive | Independent analog input/output of channel B (Y0B), switched to common pin ZB when selected by A0/A1 with E low. |
| 2 | Y2B | passive | Independent analog input/output of channel B (Y2B), switched to common pin ZB when selected by A0/A1 with E low. |
| 3 | ZB | passive | Common analog input/output of channel B, connected to one of Y0B-Y3B through the selected bidirectional switch. |
| 4 | Y3B | passive | Independent analog input/output of channel B (Y3B), switched to common pin ZB when selected by A0/A1 with E low. |
| 5 | Y1B | passive | Independent analog input/output of channel B (Y1B), switched to common pin ZB when selected by A0/A1 with E low. |
| 6 | E | input | Active-low enable input (printed with overbar in the datasheet); when high, all switches are off (high-impedance) regardless of A0/A1. |
| 7 | VEE | power_in | Negative supply voltage; recommended range -6.0 V to 0 V, and analog I/O swings between VEE and VDD. |
| 8 | VSS | power_in | Ground (digital control reference); VSS and VEE are tied together when used as a digital multiplexer. |
| 9 | A1 | input | Channel select input A1 (binary weight 2), with A0 choosing one of the four switch pairs; digital levels referenced to VDD and VSS. |
| 10 | A0 | input | Channel select input A0 (binary weight 1), with A1 choosing one of the four switch pairs; digital levels referenced to VDD and VSS. |
| 11 | Y3A | passive | Independent analog input/output of channel A (Y3A), switched to common pin ZA when selected by A0/A1 with E low. |
| 12 | Y0A | passive | Independent analog input/output of channel A (Y0A), switched to common pin ZA when selected by A0/A1 with E low. |
| 13 | ZA | passive | Common analog input/output of channel A, connected to one of Y0A-Y3A through the selected bidirectional switch. |
| 14 | Y1A | passive | Independent analog input/output of channel A (Y1A), switched to common pin ZA when selected by A0/A1 with E low. |
| 15 | Y2A | passive | Independent analog input/output of channel A (Y2A), switched to common pin ZA when selected by A0/A1 with E low. |
| 16 | VDD | power_in | Positive supply voltage; recommended 3.0 V to 18.0 V (VDD-VEE 5.0 V to 15.0 V), absolute maximum VDD -0.5 V to +18 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VDD | -0.5 |  | 18 | V |  | 5 |
| Supply voltage range VDD-VEE | VDD- VEE | -0.5 |  | 18 | V |  | 5 |
| Static current | IQ |  |  | 2 | μA | VDD-VEE=12V | 5 |
| Input voltage range (lower limit) | VI | -0.5 |  |  | V |  | 5 |
| High-level input current | /IIH/ |  |  | 1 | μA | VDD=5V, VI=VDD | 5 |
| Low-level input current | /IIL/ |  |  | 1 | μA | VDD=5V, VI=0V | 5 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI<-0.5V or VI>VDD+0.5V | 5 |
| Input/output clamp current | IIOK | -20 |  | 20 | mA | VIO<VEE-0.5V or VIO>VDD+0.5V | 5 |
| Switch on-state current | IT | -25 |  | 25 | mA | VO=-0.5V～VDD+0.5V | 5 |
| VDD or GND current | IDD, IGND | -50 |  | 50 | mA |  | 5 |
| Power dissipation | PD |  |  | 500 | mW |  | 5 |
| Storage temperature | TSTG | -65 |  | 150 | ℃ |  | 5 |
| Operating temperature | TOP | -40 |  | 85 | ℃ |  | 5 |
| Supply voltage | VDD | 3 | 5 | 18 | V |  | 5 |
| Supply voltage | VEE | -6 |  | 0 | V |  | 5 |
| Supply voltage VDD-VEE | VDD- VEE | 5 |  | 15 | V |  | 5 |
| Input voltage | VI | 0 |  |  | V |  | 5 |
| Input rise/fall time | tr,tf |  |  | 1000 | ns | VCC=3.0V | 5 |
| Input rise/fall time | tr,tf |  |  | 500 | ns | VCC=5.0V | 5 |
| Input rise/fall time | tr,tf |  |  | 400 | ns | VCC=6.0V | 5 |
| Operating temperature | TOP | -40 |  | 85 | ℃ |  | 5 |
| On-resistance | RON |  | 350 | 2500 | Ω | VDD-VEE=5V; Vis=0～VDD－VEE; see Fig.1 | 6 |
| On-resistance | RON |  | 80 | 245 | Ω | VDD-VEE=9V; Vis=0～VDD－VEE; see Fig.1 | 6 |
| On-resistance | RON |  | 115 | 340 | Ω | VDD-VEE=5V; Vis=0; see Fig.1 | 6 |
| On-resistance | RON |  | 50 | 160 | Ω | VDD-VEE=9V; Vis=0; see Fig.1 | 6 |
| On-resistance | RON |  | 120 | 365 | Ω | VDD-VEE=5V; Vis=VDD－VEE; see Fig.1 | 6 |
| On-resistance | RON |  | 65 | 200 | Ω | VDD-VEE=9V; Vis=VDD－VEE; see Fig.1 | 6 |
| Off-state leakage current (all channels off) | IOZZ |  |  | 1000 | nA | VDD-VEE=9V; all channels off; inhibit input at VDD | 6 |
| Off-state leakage current (any channel) | IOZY |  |  | 200 | nA | VDD-VEE=9V; any channel off; inhibit input at VEE | 6 |
| Transmission delay high-to-low, Vis to Vos | tPHL |  | 10 | 20 | ns | VDD=5V; Note 1: RL=10kΩ to VEE, CL=50pF to VEE, E=VSS, Vis=VDD | 8 |
| Transmission delay high-to-low, Vis to Vos | tPHL |  | 5 | 10 | ns | VDD=9V; Note 1: RL=10kΩ to VEE, CL=50pF to VEE, E=VSS, Vis=VDD | 8 |
| Transmission delay low-to-high, Vis to Vos | tPLH |  | 10 | 20 | ns | VDD=5V; Note 1: RL=10kΩ to VEE, CL=50pF to VEE, E=VSS, Vis=VDD | 8 |
| Transmission delay low-to-high, Vis to Vos | tPLH |  | 5 | 10 | ns | VDD=9V; Note 1: RL=10kΩ to VEE, CL=50pF to VEE, E=VSS, Vis=VDD | 8 |
| Transmission delay high-to-low, An to Vos | tPHL |  | 150 | 305 | ns | VDD=5V; Note 2: RL=10kΩ; CL=50pF to VEE; An=VDD square wave | 8 |
| Transmission delay high-to-low, An to Vos | tPHL |  | 65 | 135 | ns | VDD=9V; Note 2: RL=10kΩ; CL=50pF to VEE; An=VDD square wave | 8 |
| Transmission delay low-to-high, An to Vos | tPLH |  | 150 | 300 | ns | VDD=5V; Note 2: RL=10kΩ; CL=50pF to VEE; An=VDD square wave | 8 |
| Transmission delay low-to-high, An to Vos | tPLH |  | 75 | 150 | ns | VDD=9V; Note 2: RL=10kΩ; CL=50pF to VEE; An=VDD square wave | 8 |
| Output disable time high, E to Vos | tPHZ |  | 95 | 190 | ns | VDD=5V; Note 3, see Fig.3 | 8 |
| Output disable time high, E to Vos | tPHZ |  | 90 | 180 | ns | VDD=9V; Note 3, see Fig.3 | 8 |
| Output disable time low, E to Vos | tPLZ |  | 100 | 205 | ns | VDD=5V; Note 3, see Fig.3 | 8 |
| Output disable time low, E to Vos | tPLZ |  | 90 | 180 | ns | VDD=9V; Note 3, see Fig.3 | 8 |
| Output enable time high, E to Vos | tPZH |  | 130 | 260 | ns | VDD=5V; Note 3, see Fig.3 | 8 |
| Output enable time high, E to Vos | tPZH |  | 55 | 115 | ns | VDD=9V; Note 3, see Fig.3 | 8 |
| Output enable time low, E to Vos | tPZL |  | 120 | 240 | ns | VDD=5V; Note 3, see Fig.3 | 8 |
| Output enable time low, E to Vos | tPZL |  | 50 | 100 | ns | VDD=9V; Note 3, see Fig.3 | 8 |

## CAD (KiCad official)

- Symbol: `CD4052BPWRG`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `cd4052bpwrg-etched.step` / `cd4052bpwrg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4052bpwrg.step` / `cd4052bpwrg.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HANSCHIP semiconductor datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586209359872974848) (13 pp, sha256 `c277114694532f3e`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4052bpwrg-datasheet.pdf)