component
CD4052BDTR
Public Made by Adomby adom
XBLW Analog Switches, Multiplexers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4052BDTR
XBLW · Analog Switches, Multiplexers · SOP-16
CD4052BDTR from XBLW, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 2Y0 | bidirectional | Independent input or output of multiplexer 2, channel 0 (analog switch to 2Z). |
| 2 | 2Y2 | bidirectional | Independent input or output of multiplexer 2, channel 2 (analog switch to 2Z). |
| 3 | 2Z | bidirectional | Common output or input of multiplexer 2. |
| 4 | 2Y3 | bidirectional | Independent input or output of multiplexer 2, channel 3 (analog switch to 2Z). |
| 5 | 2Y1 | bidirectional | Independent input or output of multiplexer 2, channel 1 (analog switch to 2Z). |
| 6 | E | input | Active-LOW enable input; when HIGH all switches are off regardless of S1 and S2. |
| 7 | VEE | power_in | Negative supply voltage for the analog switches, recommended -6.0 V to 0 V; connect to VSS for digital multiplexing. |
| 8 | VSS | power_in | Ground (0 V). |
| 9 | S2 | input | Channel select input S2, common to both multiplexers. |
| 10 | S1 | input | Channel select input S1, common to both multiplexers. |
| 11 | 1Y3 | bidirectional | Independent input or output of multiplexer 1, channel 3 (analog switch to 1Z). |
| 12 | 1Y0 | bidirectional | Independent input or output of multiplexer 1, channel 0 (analog switch to 1Z). |
| 13 | 1Z | bidirectional | Common output or input of multiplexer 1. |
| 14 | 1Y1 | bidirectional | Independent input or output of multiplexer 1, channel 1 (analog switch to 1Z). |
| 15 | 1Y2 | bidirectional | Independent input or output of multiplexer 1, channel 2 (analog switch to 1Z). |
| 16 | VDD | power_in | Positive supply voltage, 3 V to 9 V recommended (absolute max +12 V); VDD-VEE may not exceed 9 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XBLW |
| Package | SOP-16 |
| Category | Interface |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4052BDTR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4052bdtr-etched.step/cd4052bdtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4052bdtr.step/cd4052bdtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XBLW datasheet (18 pp, sha256
ccc926f705130787, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).