component

CD4052BDRG

Public Made by Adom

by adom

HANSCHIP semiconductor Analog Switches, Multiplexers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfacecd4052bdrgfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cd4052bdrg / README.md
History Download
Ray Publish 0.1.0 17c3ad9 17d ago

CD4052BDRG

HANSCHIP semiconductor · Analog Switches, Multiplexers · SOP-16

CD4052BDRG from HANSCHIP semiconductor, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Y0B passive Independent analog input/output Y0 of switch set B; conducts to common terminal ZB when A1=L, A0=L and E is low.
2 Y2B passive Independent analog input/output Y2 of switch set B; conducts to common terminal ZB when A1=H, A0=L and E is low.
3 ZB passive Common analog input/output of switch set B; connects to the selected Y channel (Y0B to Y3B) when E is low, and is high-impedance off when E is high.
4 Y3B passive Independent analog input/output Y3 of switch set B; conducts to common terminal ZB when A1=H, A0=H and E is low.
5 Y1B passive Independent analog input/output Y1 of switch set B; conducts to common terminal ZB when A1=L, A0=H and E is low.
6 E input Active-low enable input; when low the channel selected by A0/A1 is on, and when high all switches are off regardless of A0/A1.
7 VEE power_in Negative supply; recommended range -6.0 V to 0 V, and tied to VSS when the device is used as a digital multiplexer (typically grounded).
8 VSS power_in Ground reference for the digital control inputs A0, A1 and E, normally connected to 0 V.
9 A1 input Select input 1 of the channel decoder; selects among Y0 to Y3 together with A0 when E is low.
10 A0 input Select input 0 of the channel decoder; selects among Y0 to Y3 together with A1 when E is low.
11 Y3A passive Independent analog input/output Y3 of switch set A; conducts to common terminal ZA when A1=H, A0=H and E is low.
12 Y0A passive Independent analog input/output Y0 of switch set A; conducts to common terminal ZA when A1=L, A0=L and E is low.
13 ZA passive Common analog input/output of switch set A; connects to the selected Y channel (Y0A to Y3A) when E is low, and is high-impedance off when E is high.
14 Y1A passive Independent analog input/output Y1 of switch set A; conducts to common terminal ZA when A1=L, A0=H and E is low.
15 Y2A passive Independent analog input/output Y2 of switch set A; conducts to common terminal ZA when A1=H, A0=L and E is low.
16 VDD power_in Positive supply; recommended range 3.0 V to 18.0 V, with VDD−VEE between 5.0 V and 15.0 V, and the analog I/O range extends up to VDD.

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package SOP-16
Category Interface
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range (VDD) VDD -0.5 18 V 5
Supply voltage range (VDD-VEE) VDD-VEE -0.5 18 V 5
Static current IQ 2 μA VDD-VEE=12V 5
Input voltage range VI -0.5 V 5
High-level input current /IIH/ 1 μA VDD=5V, VI=VDD 5
Low-level input current /IIL/ 1 μA VDD=5V, VI=0V 5
Input clamp current IIK -20 20 mA VI<-0.5V or VI>VDD+0.5V 5
Input/output clamp current IIOK -20 20 mA VIO<VEE-0.5V or VIO>VDD+0.5V 5
Switch on-state current IT -25 25 mA VO=-0.5V to VDD+0.5V 5
VDD or GND current IDD, IGND -50 50 mA 5
Power dissipation PD 500 mW 5
Storage temperature TSTG -65 150 ℃ 5
Soldering temperature TL 245 ℃ 10 s; SOP package 5
Supply voltage (VDD) VDD 3 5 18 V 5
Supply voltage (VEE) VEE -6 0 V 5
Supply voltage (VDD-VEE) VDD-VEE 5 15 V 5
Input voltage VI 0 V 5
Input rise/fall time tr,tf 1000 ns VCC=3.0V 5
Input rise/fall time tr,tf 500 ns VCC=5.0V 5
Input rise/fall time tr,tf 400 ns VCC=6.0V 5
Operating temperature TOP -40 85 ℃ 5
On-resistance RON 350 2500 Ω VDD-VEE=5V; Vis=0～VDD－VEE; see Fig.1 6
On-resistance RON 80 245 Ω VDD-VEE=9V; Vis=0～VDD－VEE; see Fig.1 6
On-resistance RON 115 340 Ω VDD-VEE=5V; Vis=0; see Fig.1 6
On-resistance RON 50 160 Ω VDD-VEE=9V; Vis=0; see Fig.1 6
On-resistance RON 120 365 Ω VDD-VEE=5V; Vis=VDD-VEE; see Fig.1 6
On-resistance RON 65 200 Ω VDD-VEE=9V; Vis=VDD-VEE; see Fig.1 6
Off-state leakage current (all channels off) IOZZ 1000 nA VDD-VEE=9V; E at VDD 6
Off-state leakage current (any channel off) IOZY 200 nA VDD-VEE=9V; E at VEE 6
Propagation delay Vis to Vos (high to low) tPHL 10 20 ns VDD=5V; note 1: RL=10kΩ to VEE; CL=50pF to VEE; E=VSS; Vis=VDD square wave 8
Propagation delay Vis to Vos (high to low) tPHL 5 10 ns VDD=9V; note 1: RL=10kΩ to VEE; CL=50pF to VEE; E=VSS; Vis=VDD square wave 8
Propagation delay Vis to Vos (low to high) tPLH 10 20 ns VDD=5V; note 1: RL=10kΩ to VEE; CL=50pF to VEE; E=VSS; Vis=VDD square wave 8
Propagation delay Vis to Vos (low to high) tPLH 5 10 ns VDD=9V; note 1: RL=10kΩ to VEE; CL=50pF to VEE; E=VSS; Vis=VDD square wave 8
Propagation delay An to Vos (high to low) tPHL 150 305 ns VDD=5V; note 2: RL=10kΩ; CL=50pF to VEE; E=VSS; An=VDD square wave 8
Propagation delay An to Vos (high to low) tPHL 65 135 ns VDD=9V; note 2: RL=10kΩ; CL=50pF to VEE; E=VSS; An=VDD square wave 8
Propagation delay An to Vos (low to high) tPLH 150 300 ns VDD=5V; note 2: RL=10kΩ; CL=50pF to VEE; E=VSS; An=VDD square wave 8
Propagation delay An to Vos (low to high) tPLH 75 150 ns VDD=9V; note 2: RL=10kΩ; CL=50pF to VEE; E=VSS; An=VDD square wave 8
Output disable time, high (E to Vos) tPHZ 95 190 ns VDD=5V; note 3 (see Fig.3) 8
Output disable time, high (E to Vos) tPHZ 90 180 ns VDD=9V; note 3 (see Fig.3) 8
Output disable time, low (E to Vos) tPLZ 100 205 ns VDD=5V; note 3 (see Fig.3) 8
Output disable time, low (E to Vos) tPLZ 90 180 ns VDD=9V; note 3 (see Fig.3) 8
Output enable time, high (E to Vos) tPZH 130 260 ns VDD=5V; note 3 (see Fig.3) 8
Output enable time, high (E to Vos) tPZH 55 115 ns VDD=9V; note 3 (see Fig.3) 8
Output enable time, low (E to Vos) tPZL 120 240 ns VDD=5V; note 3 (see Fig.3) 8
Output enable time, low (E to Vos) tPZL 50 100 ns VDD=9V; note 3 (see Fig.3) 8

CAD (KiCad official)

  • Symbol: CD4052BDRG
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4052bdrg-etched.step / cd4052bdrg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4052bdrg.step / cd4052bdrg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (13 pp, sha256 c277114694532f3e, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF