component
CD4051BPWRG
Public Made by Adomby adom
HANSCHIP semiconductor Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 11d ago |
| viewers | 11d ago |
| cd4051bpwrg-etched.glb | 11d ago |
| cd4051bpwrg-etched.step | 11d ago |
| cd4051bpwrg-hero.glb | 11d ago |
| cd4051bpwrg-hero.overlay.json | 11d ago |
| cd4051bpwrg.glb | 11d ago |
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CD4051BPWRG
HANSCHIP semiconductor · Analog Switches, Multiplexers · TSSOP-16
CD4051BPWRG from HANSCHIP semiconductor, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y4 | bidirectional | Independent analog input/output channel 4 that connects to common Z when selected by A0-A2 with E low; analog signals must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 2 | Y6 | bidirectional | Independent analog input/output channel 6 that connects to common Z when selected by A0-A2 with E low; analog signals must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 3 | Z | bidirectional | Common analog input/output that connects to whichever Y channel is selected; voltage must not exceed VDD or fall below VEE and switch current is limited to ±10 mA. |
| 4 | Y7 | bidirectional | Independent analog input/output channel 7 that connects to common Z when selected by A0-A2 with E low; analog signals must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 5 | Y5 | bidirectional | Independent analog input/output channel 5 that connects to common Z when selected by A0-A2 with E low; analog signals must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 6 | E | input | Active-low enable input: when low the channel selected by A0-A2 is switched on, and when high all switches are off (high impedance); input range is 0 to VDD. |
| 7 | VEE | power_in | Negative supply for the analog switches; absolute maximum is -18 V to +0.5 V referenced to VSS, recommended range -6.0 V to 0 V, and it must be tied to VSS (ground) for digital multiplexing use. |
| 8 | VSS | power_in | Ground and reference for the digital control inputs A0-A2 and E; 0 V is the reference used for the electrical characteristics. |
| 9 | A2 | input | Channel-select address input (bit 2) that, with A0 and A1, selects which Y channel connects to Z while E is low; input range is 0 to VDD. |
| 10 | A1 | input | Channel-select address input (bit 1) that, with A0 and A2, selects which Y channel connects to Z while E is low; input range is 0 to VDD. |
| 11 | A0 | input | Channel-select address input (bit 0) that, with A1 and A2, selects which Y channel connects to Z while E is low; input range is 0 to VDD. |
| 12 | Y3 | bidirectional | Independent analog input/output channel 3 that connects to common Z when selected by A0-A2 with E low; analog signals must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 13 | Y0 | bidirectional | Independent analog input/output channel 0 that connects to common Z when selected by A0-A2 with E low; analog signals must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 14 | Y1 | bidirectional | Independent analog input/output channel 1 that connects to common Z when selected by A0-A2 with E low; analog signals must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 15 | Y2 | bidirectional | Independent analog input/output channel 2 that connects to common Z when selected by A0-A2 with E low; analog signals must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 16 | VDD | power_in | Positive supply for the digital inputs and analog switches; absolute maximum is -0.5 V to +18 V referenced to VSS, with a recommended VDD of 3.0 V to 18 V and VDD−VEE of 5 V to 15 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4051BPWRG - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4051bpwrg-etched.step/cd4051bpwrg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4051bpwrg.step/cd4051bpwrg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HANSCHIP semiconductor datasheet (17 pp, sha256
2dc48e395c8369b1, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).