component
CD4051BM-MS
Public Made by Adomby adom
MSKSEMI Analog Switches, Multiplexers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4051BM-MS
MSKSEMI · Analog Switches, Multiplexers · SOP-16
CD4051BM-MS from MSKSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 4 | passive | Analog switch channel 4 terminal; analog signal must stay within 0 to VDD-VEE (0 to 15 V). |
| 2 | 6 | passive | Analog switch channel 6 terminal; analog signal must stay within 0 to VDD-VEE (0 to 15 V). |
| 3 | COM | passive | Common analog input/output terminal of the single-pole eight-throw switch; analog signal must stay within 0 to VDD-VEE (0 to 15 V). |
| 4 | 7 | passive | Analog switch channel 7 terminal; analog signal must stay within 0 to VDD-VEE (0 to 15 V). |
| 5 | 5 | passive | Analog switch channel 5 terminal; analog signal must stay within 0 to VDD-VEE (0 to 15 V). |
| 6 | INH | input | Inhibit/enable control: per the truth table, INH high (1) turns all channels off, and INH low (0) enables the channel selected by A, B, C. |
| 7 | VEE | power_in | Analog switch negative supply; VDD-VEE must be within 0 to 15 V. |
| 8 | VSS | power_in | Digital ground/supply reference; VDD-VSS must be within 3 to 15 V and control input voltage within 0 to VDD-VSS. |
| 9 | C | input | Binary channel-select control input C; control input voltage must stay within 0 to VDD-VSS. |
| 10 | B | input | Binary channel-select control input B; control input voltage must stay within 0 to VDD-VSS. |
| 11 | A | input | Binary channel-select control input A; control input voltage must stay within 0 to VDD-VSS. |
| 12 | 3 | passive | Analog switch channel 3 terminal; analog signal must stay within 0 to VDD-VEE (0 to 15 V). |
| 13 | 0 | passive | Analog switch channel 0 terminal; analog signal must stay within 0 to VDD-VEE (0 to 15 V). |
| 14 | 1 | passive | Analog switch channel 1 terminal; analog signal must stay within 0 to VDD-VEE (0 to 15 V). |
| 15 | 2 | passive | Analog switch channel 2 terminal; analog signal must stay within 0 to VDD-VEE (0 to 15 V). |
| 16 | VDD | power_in | Positive supply; VDD-VSS must be within 3 to 15 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MSKSEMI |
| Package | SOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage (VDD-VSS), absolute maximum | VDD-VSS | -0.5 | 18 | V | 3 | ||
| Analog supply voltage (VDD-VEE), absolute maximum | VDD-VEE | 18 | V | 3 | |||
| Power dissipation | PD | 500 | mW | 3 | |||
| Operating temperature, absolute maximum | TA | -40 | 85 | ℃ | 3 | ||
| Storage temperature | TS | -65 | 150 | ℃ | 3 | ||
| Lead soldering temperature | TW | 260 | ℃ | 10s | 3 | ||
| DC supply voltage (VDD-VSS), recommended | VDD-VSS | 3 | 15 | V | 4 | ||
| Control input voltage | VIS | 0 | V | Upper limit printed as VDD-VSS | 4 | ||
| Analog supply voltage (VDD-VEE), recommended | VDD-VEE | 0 | 15 | V | 4 | ||
| Analog input/output voltage | VIN, VOUT | 0 | V | Upper limit printed as VDD-VEE | 4 | ||
| Operating temperature, recommended | TA | -40 | 85 | ℃ | 4 | ||
| High-level input voltage | VIH | 3.5 | V | VDD=5V; VIH=VDD through 1k; VEE=VSS; RL=1kΩ to VSS; IIS<2uA on all OFF channels | 4 | ||
| High-level input voltage | VIH | 7 | V | VDD=10V; VIH=VDD through 1k; VEE=VSS; RL=1kΩ to VSS; IIS<2uA on all OFF channels | 4 | ||
| High-level input voltage | VIH | 11 | V | VDD=15V; VIH=VDD through 1k; VEE=VSS; RL=1kΩ to VSS; IIS<2uA on all OFF channels | 4 | ||
| Low-level input voltage | VIL | 1.5 | V | VDD=5V; VIL=VDD through 1k | 4 | ||
| Low-level input voltage | VIL | 3 | V | VDD=10V; VIL=VDD through 1k | 4 | ||
| Low-level input voltage | VIL | 4 | V | VDD=15V; VIL=VDD through 1k | 4 | ||
| Channel-to-channel ON resistance difference | △RON | 15 | Ω | VDD=5V; adjacent channels | 4 | ||
| Channel-to-channel ON resistance difference | △RON | 10 | Ω | VDD=10V; adjacent channels | 4 | ||
| Channel-to-channel ON resistance difference | △RON | 5 | Ω | VDD=15V; adjacent channels | 4 | ||
| Off-channel leakage current | IOFF | -100 | 100 | nA | Input/output channels OFF, INH=VDD; VDD=18V | 4 | |
| Input current | IIN | -0.1 | 0.01 | 0.1 | uA | VIN=VDD or VSS; VDD=18V | 4 |
| Quiescent supply current | IDD | 0.01 | 5 | uA | VIN=VDD or VSS; VDD=5V | 4 | |
| Quiescent supply current | IDD | 0.01 | 10 | uA | VIN=VDD or VSS; VDD=10V | 4 | |
| Quiescent supply current | IDD | 0.01 | 20 | uA | VIN=VDD or VSS; VDD=15V | 4 | |
| Propagation delay, signal input to output | tpd | 15 | ns | VIS=VDD; RL=200kΩ; CL=50pF; VDD=5V | 4 | ||
| Propagation delay, signal input to output | tpd | 10 | ns | VIS=VDD; RL=200kΩ; CL=50pF; VDD=10V | 4 | ||
| Propagation delay, signal input to output | tpd | 7 | ns | VIS=VDD; RL=200kΩ; CL=50pF; VDD=15V | 4 | ||
| Propagation delay, address-to-signal output (channels ON or OFF) | tpd | 100 | ns | CL=50pF; RL=10kΩ; VDD=5V | 4 | ||
| Propagation delay, address-to-signal output (channels ON or OFF) | tpd | 80 | ns | CL=50pF; RL=10kΩ; VDD=10V | 4 | ||
| Propagation delay, address-to-signal output (channels ON or OFF) | tpd | 50 | ns | CL=50pF; RL=10kΩ; VDD=15V | 4 | ||
| Propagation delay, inhibit-to-signal output (channel turning ON) | tpd | 100 | ns | CL=50pF; RL=1kΩ; VDD=5V | 5 | ||
| Propagation delay, inhibit-to-signal output (channel turning ON) | tpd | 50 | ns | CL=50pF; RL=1kΩ; VDD=10V | 5 | ||
| Propagation delay, inhibit-to-signal output (channel turning ON) | tpd | 30 | ns | CL=50pF; RL=1kΩ; VDD=15V | 5 | ||
| Propagation delay, inhibit-to-signal output (channel turning OFF) | tpd | 100 | ns | CL=50pF; RL=10kΩ; VDD=5V | 5 | ||
| Propagation delay, inhibit-to-signal output (channel turning OFF) | tpd | 50 | ns | CL=50pF; RL=10kΩ; VDD=10V | 5 | ||
| Propagation delay, inhibit-to-signal output (channel turning OFF) | tpd | 30 | ns | CL=50pF; RL=10kΩ; VDD=15V | 5 |
CAD (KiCad official)
- Symbol:
CD4051BM-MS - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4051bm-ms-etched.step/cd4051bm-ms-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4051bm-ms.step/cd4051bm-ms.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MSKSEMI datasheet (9 pp, sha256
572c38b9e18a17c9, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).