component

CD4050BDR

Public Made by Adom

by adom

Texas Instruments Buffer/Driver/Transceiver, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4050bdr
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cd4050bdr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
cd4050bdr-etched.fit.json cd4050bdr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
cd4050bdr-etched.glb cd4050bdr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body w… · Ray 14d ago
cd4050bdr-etched.step cd4050bdr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body w… · Ray 14d ago
cd4050bdr.glb Publish 0.1.0 · Ray 2mo ago
cd4050bdr.kicad_mod Publish 0.1.0 · Ray 2mo ago
cd4050bdr.kicad_sym Publish 0.1.0 · Ray 2mo ago
cd4050bdr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray 2mo ago
cd4050bdr.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
page.json cd4050bdr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body w… · Ray 14d ago
README.md cd4050bdr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

CD4050BDR

Texas Instruments · Buffer/Driver/Transceiver · SOIC-16

CD4050BDR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Positive supply voltage. Recommended operating range 3 V to 18 V; absolute max 20 V referenced to VSS.
2 G output Non-inverting buffer output 1 (G = A). Drives up to 2 TTL loads; typical IOL ≥ 3.3 mA at VOL ≤ 0.4 V with VCC = 5 V.
3 A input Buffer input 1. High-impedance CMOS input; VIH may exceed VCC (up to 15 V regardless of VCC), enabling logic-level down-conversion.
4 H output Non-inverting buffer output 2 (H = B).
5 B input Buffer input 2. High-impedance CMOS input; VIH may exceed VCC.
6 I output Non-inverting buffer output 3 (I = C).
7 C input Buffer input 3. High-impedance CMOS input; VIH may exceed VCC.
8 VSS power_in Negative supply / ground reference (0 V in single-supply operation).
9 D input Buffer input 4. High-impedance CMOS input; VIH may exceed VCC.
10 J output Non-inverting buffer output 4 (J = D).
11 E input Buffer input 5. High-impedance CMOS input; VIH may exceed VCC.
12 K output Non-inverting buffer output 5 (K = E).
13 NC unconnected No internal connection. Leave floating or tie to VSS/VCC per board practice.
14 F input Buffer input 6. High-impedance CMOS input; VIH may exceed VCC.
15 L output Non-inverting buffer output 6 (L = F).
16 NC unconnected No internal connection.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • CD4050BDRD
  • CD4050BDR
  • CD4050BDRDW
  • CD4050BDRDWR
  • CD4050BDRE
  • CD4050BDRNS
  • CD4050BDRNSR
  • CD4050BDRPW
  • CD4050BDRPWR

CAD (KiCad official)

  • Symbol: CD4050BDR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd4050bdr-etched.step / cd4050bdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4050bdr.step / cd4050bdr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cd4050bdr.step 217 KB You want the bare part, or you mark your own boards.
cd4050bdr-etched.step 2.5 MB You want the part with CD4050BDR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 632 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (39 pp, sha256 ee56c7e624d98e37, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF