CD4049UBDR

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4049ubdr",
  "title": "CD4049UBDR",
  "brief": "Texas Instruments Buffer/Driver/Transceiver, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4049ubdr"
  ],
  "component": {
    "mpn": "CD4049UBDR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Buffer/Driver/Transceiver",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4049ub.pdf",
    "parts": {
      "symbol": "cd4049ubdr.kicad_sym",
      "footprint": "cd4049ubdr.kicad_mod",
      "model_3d": "cd4049ubdr-etched.glb",
      "model_3d_plain": "cd4049ubdr.glb",
      "model_3d_step": "cd4049ubdr-etched.step",
      "model_3d_step_plain": "cd4049ubdr.step",
      "lbr": "cd4049ubdr.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage pin. Operates at 5V, 10V, or 15V per parametric ratings; absolute maximum VCC to VSS is 20V."
      },
      {
        "number": "2",
        "name": "G",
        "type": "output",
        "description": "Inverting buffer output 1. G = NOT(A). CMOS output capable of driving two TTL loads with VOL ≤ 0.4V at IOL ≥ 3.3mA."
      },
      {
        "number": "3",
        "name": "A",
        "type": "input",
        "description": "Logic input 1 to inverter A→G. Input high-level (VIH) may exceed VCC for high-to-low level conversion. Maximum input current 1µA at 18V."
      },
      {
        "number": "4",
        "name": "H",
        "type": "output",
        "description": "Inverting buffer output 2. H = NOT(B). CMOS output capable of driving two TTL loads."
      },
      {
        "number": "5",
        "name": "B",
        "type": "input",
        "description": "Logic input 2 to inverter B→H. Input high-level may exceed VCC for level shifting."
      },
      {
        "number": "6",
        "name": "I",
        "type": "output",
        "description": "Inverting buffer output 3. I = NOT(C). CMOS output capable of driving two TTL loads."
      },
      {
        "number": "7",
        "name": "C",
        "type": "input",
        "description": "Logic input 3 to inverter C→I. Input high-level may exceed VCC for level shifting."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference for the device."
      },
      {
        "number": "9",
        "name": "D",
        "type": "input",
        "description": "Logic input 4 to inverter D→J. Input high-level may exceed VCC for level shifting."
      },
      {
        "number": "10",
        "name": "J",
        "type": "output",
        "description": "Inverting buffer output 4. J = NOT(D). CMOS output capable of driving two TTL loads."
      },
      {
        "number": "11",
        "name": "E",
        "type": "input",
        "description": "Logic input 5 to inverter E→K. Input high-level may exceed VCC for level shifting."
      },
      {
        "number": "12",
        "name": "K",
        "type": "output",
        "description": "Inverting buffer output 5. K = NOT(E). CMOS output capable of driving two TTL loads."
      },
      {
        "number": "13",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection. Leave floating or tie as needed."
      },
      {
        "number": "14",
        "name": "F",
        "type": "input",
        "description": "Logic input 6 to inverter F→L. Input high-level may exceed VCC for level shifting."
      },
      {
        "number": "15",
        "name": "L",
        "type": "output",
        "description": "Inverting buffer output 6. L = NOT(F). CMOS output capable of driving two TTL loads."
      },
      {
        "number": "16",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection. Leave floating or tie as needed."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cd4049ub.pdf",
        "pages": 39,
        "sha256": "ee56c7e624d98e37",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "CD4049",
      "logic_family": "CD4000",
      "function_code": "4049",
      "function_class": "Buffer",
      "function_name": "Hex Inverting Buffer / Level Translator",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "cd4049ubdr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4049ubdr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "1f29ec028a6be77e823bf2b8e2fca7e936e87ee3e9a0423956698ff439abd24c",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd4049ubdr"
  ],
  "discovery_pitch": "CD4049UBDR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4049ubdr.kicad_sym",
    "cd4049ubdr.kicad_mod",
    "cd4049ubdr.glb",
    "cd4049ubdr.step",
    "cd4049ubdr-etched.step",
    "cd4049ubdr.lbr",
    "docs/hero.png",
    "docs/cd4049ubdr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "CD4049UBDRD",
      "kind": "packaging"
    },
    {
      "mpn": "CD4049UBDR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4049UBDRE",
      "kind": "packaging"
    },
    {
      "mpn": "CD4049UBDRDW",
      "kind": "packaging"
    },
    {
      "mpn": "CD4049UBDRDWR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4049UBDRNS",
      "kind": "packaging"
    },
    {
      "mpn": "CD4049UBDRNSR",
      "kind": "packaging"
    },
    {
      "mpn": "CD4049UBDRPW",
      "kind": "packaging"
    },
    {
      "mpn": "CD4049UBDRPWR",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T18:41:51.675Z"
}