main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 6h ago
viewers cd4047be: viewers · Ray 6h ago
cd4047be-etched.glb cd4047be: factory component page (tier=lcsc) · Ray 6h ago
cd4047be-etched.step cd4047be: factory component page (tier=lcsc) · Ray 6h ago
cd4047be-hero.glb Publish 0.1.0 · Ray 6h ago
cd4047be-hero.overlay.json Publish 0.1.0 · Ray 6h ago
cd4047be.glb Publish 0.1.0 · Ray 6h ago
cd4047be.kicad_mod Publish 0.1.0 · Ray 6h ago
cd4047be.kicad_sym Publish 0.1.0 · Ray 6h ago
cd4047be.lbr Publish 0.1.0 · Ray 6h ago
cd4047be.step Publish 0.1.0 · Ray 6h ago
package.json Publish 0.1.0 · Ray 6h ago
page.json Set visibility: public · Ray 6h ago
README.md Initial commit: component/cd4047be · Ray 6h ago

CD4047BE

Texas Instruments · Monostable Multivibrators · DIP-14

CD4047BE from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 C passive C-timing terminal; the external timing capacitor connects between this pin and RC-Common (pin 3).
2 R passive R-timing terminal; the external timing resistor connects between this pin and RC-Common (pin 3).
3 RC COMMON passive Common node of the external R and C; the datasheet cautions this terminal is more sensitive to static electrical discharge and needs extra handling precautions.
4 ASTABLE (active-low) input Astable input (overbar on the pin name); a low level enables astable operation, and a high level is used for monostable and true-gating modes.
5 ASTABLE input Astable input; a high level enables astable operation, and a low level is used for complement gating and monostable modes.
6 -TRIGGER input Negative-edge trigger input for monostable operation, held high (VDD) for positive-edge triggering or when unused in astable modes; input range is -0.5 V to VDD+0.5 V.
7 VSS power_in Negative supply terminal (ground); all voltage ratings are referenced to VSS.
8 +TRIGGER input Positive-edge trigger input for monostable operation; input range is -0.5 V to VDD+0.5 V.
9 EXT RESET input External reset input; a high level ensures no output pulse during power-on and can terminate the output pulse at any time.
10 Q output True buffered output (from the divide-by-2 stage) with sink current of 0.51 mA min at 5 V and 3.4 mA min at 15 V (+25 C).
11 Q̅ output Complemented buffered output, a buffered output of the divide-by-2 stage.
12 RETRIGGER input Retrigger input; when high the monostable output pulse is retriggerable (positive-going edge only), and it is tied to VSS for non-retriggered modes.
13 OSC OUT output Buffered oscillator output, with a period half that of the Q output in astable mode and no guaranteed 50% duty cycle.
14 VDD power_in Positive supply terminal; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: CD4047BE
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4047be-etched.step / cd4047be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4047be.step / cd4047be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 51d8936d15b6b0b3, retrieved 2026-10-06, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF