CD4046B Phase-Locked Loop

@@ -1,8 +1,11 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4046",+  "title": "CD4046B Phase-Locked Loop",+  "brief": "Micropower CMOS phase-locked loop with a VCO and two phase comparators.",   "version": "0.1.0",-  "type": "component",-  "description": "Micropower CMOS phase-locked loop with a VCO and two phase comparators.",+  "license": "CC-BY-SA-4.0",   "tags": [     "pll",     "phase-locked-loop",@@ -12,6 +15,168 @@     "ti",     "soic-16"   ],+  "component": {+    "mpn": "CD4046B",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-16",+    "pin_count": 16,+    "category": "Analog",+    "subcategory": "Phase-Locked Loop (PLL)",+    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4046b.pdf",+    "parts": {+      "symbol": "cd4046.kicad_sym",+      "footprint": "cd4046.kicad_mod",+      "model_3d": "cd4046.glb"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "PHASE_PULSES",+        "type": "output",+        "description": "Phase pulses output; goes high when the PLL is out of lock and is used as a phase-lock indicator (particularly with phase comparator II). CMOS output."+      },+      {+        "number": "2",+        "name": "PHASE_COMP_I_OUT",+        "type": "output",+        "description": "Output of phase comparator I (exclusive-OR network). Feeds the external low-pass filter that drives the VCO. CMOS rail-to-rail output."+      },+      {+        "number": "3",+        "name": "COMPARATOR_IN",+        "type": "input",+        "description": "Comparator input to both phase comparators. Typically driven from the loop's frequency divider or directly from the VCO output for a 1:1 loop. High-impedance CMOS input."+      },+      {+        "number": "4",+        "name": "VCO_OUT",+        "type": "output",+        "description": "VCO square-wave output (50% duty cycle). CMOS rail-to-rail swing (VSS to VDD). Drives the comparator input directly or via a frequency divider."+      },+      {+        "number": "5",+        "name": "INHIBIT",+        "type": "input",+        "description": "VCO/source-follower ON/OFF control. Logic 0 enables the VCO and source follower; logic 1 turns them off for ultra-low standby power. High-impedance CMOS input."+      },+      {+        "number": "6",+        "name": "C1A",+        "type": "passive",+        "description": "VCO timing capacitor C1 terminal A. External capacitor C1 (>=50 pF at VDD>=10 V, >=100 pF at VDD=5 V) connected between C1A (pin 6) and C1B (pin 7) sets the VCO frequency together with R1/R2."+      },+      {+        "number": "7",+        "name": "C1B",+        "type": "passive",+        "description": "VCO timing capacitor C1 terminal B. Paired with C1A (pin 6). See C1A for value guidance."+      },+      {+        "number": "8",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference (0 V). All input voltages are referenced to VSS."+      },+      {+        "number": "9",+        "name": "VCO_IN",+        "type": "input",+        "description": "VCO control-voltage input (from the low-pass filter output). High input impedance (~10^12 \u03a9). Voltage on this pin sets the instantaneous VCO frequency between fmin and fmax."+      },+      {+        "number": "10",+        "name": "DEMODULATOR_OUT",+        "type": "output",+        "description": "Source-follower output of the VCO control voltage (demodulated output). Requires an external load resistor Rs >= 10 k\u03a9 to VSS; leave open if unused. Provides FM demodulation output."+      },+      {+        "number": "11",+        "name": "R1",+        "type": "passive",+        "description": "VCO frequency-setting resistor R1 terminal (connect R1 between pin 11 and VSS). 5 k\u03a9 <= R1 <= 1 M\u03a9. R1 with C1 sets fo/fmax."+      },+      {+        "number": "12",+        "name": "R2",+        "type": "passive",+        "description": "VCO frequency-offset resistor R2 terminal (connect R2 between pin 12 and VSS). 5 k\u03a9 <= R2 <= 1 M\u03a9. Sets fmin offset; leave open (R2 = \u221e) for no offset."+      },+      {+        "number": "13",+        "name": "PHASE_COMP_II_OUT",+        "type": "tri_state",+        "description": "Output of phase comparator II (edge-controlled digital memory network). Three-state output (drives high, low, or high-impedance for a locked condition). Feeds the external low-pass filter."+      },+      {+        "number": "14",+        "name": "SIGNAL_IN",+        "type": "input",+        "description": "Signal input to the on-chip self-biasing amplifier feeding both phase comparators. Can be AC-coupled for small signals or direct-coupled for CMOS-level signals. Input resistance ~1 M\u03a9 typ at VDD=5 V."+      },+      {+        "number": "15",+        "name": "ZENER",+        "type": "passive",+        "description": "Cathode of internal 5.2 V (typ, 4.45-6.15 V) zener regulator diode. Anode is VSS. Used with an external series resistor from an unregulated supply to provide a regulated supply for VDD when needed."+      },+      {+        "number": "16",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply. 3-18 V for VCO as fixed oscillator; 5-18 V for phased-lock-loop operation. Bypass to VSS with a local ceramic capacitor."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/cd4046b.pdf",+        "pages": 20,+        "sha256": "5b8f7c0b007da6cf",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Type": "Phase-locked loop (VCO + 2 phase comparators)",+      "Logic family": "4000B (CMOS)",+      "VCO frequency": "Up to ~1.4 MHz at 10 V (component set)",+      "Phase comparators": "XOR (I) and edge-triggered (II)",+      "Supply voltage": "3 V to 18 V",+      "Operating temperature": "-55 C to 125 C"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "phase-locked loop",+    "PLL",+    "frequency synthesizer",+    "clock recovery",+    "VCO"+  ],+  "discovery_pitch": "A classic CMOS PLL with an on-chip VCO for frequency multiplication, FSK demodulation, and clock recovery.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -27,10 +192,5 @@     "docs/cd4046-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file