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CD4046B Phase-Locked Loop

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by adom

Micropower CMOS phase-locked loop with a VCO and two phase comparators.

pllphase-locked-loopvcoclock4000-seriestisoic-16
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Contents

README

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CD4046B

Texas Instruments · Phase-Locked Loop (PLL) · SOIC-16

The CD4046B is a micropower CMOS phase-locked loop containing a linear voltage-controlled oscillator (VCO) and two phase comparators sharing a common signal and comparator input. It is widely used for frequency synthesis and multiplication, FM/FSK demodulation, and clock recovery from 3 V to 18 V.

Pinout

Pin Name Type Function
1 PHASE_PULSES output Phase pulses output; goes high when the PLL is out of lock and is used as a phase-lock indicator (particularly with phase comparator II). CMOS output.
2 PHASE_COMP_I_OUT output Output of phase comparator I (exclusive-OR network). Feeds the external low-pass filter that drives the VCO. CMOS rail-to-rail output.
3 COMPARATOR_IN input Comparator input to both phase comparators. Typically driven from the loop's frequency divider or directly from the VCO output for a 1:1 loop. High-impedance CMOS input.
4 VCO_OUT output VCO square-wave output (50% duty cycle). CMOS rail-to-rail swing (VSS to VDD). Drives the comparator input directly or via a frequency divider.
5 INHIBIT input VCO/source-follower ON/OFF control. Logic 0 enables the VCO and source follower; logic 1 turns them off for ultra-low standby power. High-impedance CMOS input.
6 C1A passive VCO timing capacitor C1 terminal A. External capacitor C1 (>=50 pF at VDD>=10 V, >=100 pF at VDD=5 V) connected between C1A (pin 6) and C1B (pin 7) sets the VCO frequency together with R1/R2.
7 C1B passive VCO timing capacitor C1 terminal B. Paired with C1A (pin 6). See C1A for value guidance.
8 VSS power_in Negative supply / ground reference (0 V). All input voltages are referenced to VSS.
9 VCO_IN input VCO control-voltage input (from the low-pass filter output). High input impedance (~10^12 Ω). Voltage on this pin sets the instantaneous VCO frequency between fmin and fmax.
10 DEMODULATOR_OUT output Source-follower output of the VCO control voltage (demodulated output). Requires an external load resistor Rs >= 10 kΩ to VSS; leave open if unused. Provides FM demodulation output.
11 R1 passive VCO frequency-setting resistor R1 terminal (connect R1 between pin 11 and VSS). 5 kΩ <= R1 <= 1 MΩ. R1 with C1 sets fo/fmax.
12 R2 passive VCO frequency-offset resistor R2 terminal (connect R2 between pin 12 and VSS). 5 kΩ <= R2 <= 1 MΩ. Sets fmin offset; leave open (R2 = ∞) for no offset.
13 PHASE_COMP_II_OUT tri_state Output of phase comparator II (edge-controlled digital memory network). Three-state output (drives high, low, or high-impedance for a locked condition). Feeds the external low-pass filter.
14 SIGNAL_IN input Signal input to the on-chip self-biasing amplifier feeding both phase comparators. Can be AC-coupled for small signals or direct-coupled for CMOS-level signals. Input resistance ~1 MΩ typ at VDD=5 V.
15 ZENER passive Cathode of internal 5.2 V (typ, 4.45-6.15 V) zener regulator diode. Anode is VSS. Used with an external series resistor from an unregulated supply to provide a regulated supply for VDD when needed.
16 VDD power_in Positive supply. 3-18 V for VCO as fixed oscillator; 5-18 V for phased-lock-loop operation. Bypass to VSS with a local ceramic capacitor.

Key specifications

Parameter Value
Type Phase-locked loop (VCO + 2 phase comparators)
Logic family 4000B (CMOS)
VCO frequency Up to ~1.4 MHz at 10 V (component set)
Phase comparators XOR (I) and edge-triggered (II)
Supply voltage 3 V to 18 V
Operating temperature -55 C to 125 C

Ordering variants

Same part, different packaging or reel option.

  • CD4046BE
  • CD4046BBE
  • CD4046BBEE4
  • CD4046BF3A
  • CD4046BBF
  • CD4046BBF3A
  • CD4046BF
  • CD4046BNSR
  • CD4046BNSRE4
  • CD4046BPW
  • CD4046BPWR
  • CD4046BPWG4
  • CD4046BPWRG4

CAD (KiCad official)

  • Symbol: cd4046.kicad_sym
  • Footprint: cd4046.kicad_mod
  • 3D model: SOIC-16 body from KiCad Package_SO/SOIC-16_3.9x9.9mm_P1.27mm.
  • 3D model files: cd4046-etched.step / cd4046-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4046.step / cd4046.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 5b8f7c0b007da6cf, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF