component
CD4043BE
Public Made by Adomby adom
XBLW Latches, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD4043BE
XBLW · Latches · DIP-16
CD4043BE from XBLW, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 4Q | tri_state | 3-state buffered latch output for latch 4, high impedance when OE is LOW. |
| 2 | 1Q | tri_state | 3-state buffered latch output for latch 1, high impedance when OE is LOW. |
| 3 | 1R | input | Active HIGH reset input for latch 1. |
| 4 | 1S | input | Active HIGH set input for latch 1. |
| 5 | OE | input | Common output enable input; outputs are high impedance when LOW and follow the latches when HIGH. |
| 6 | 2S | input | Active HIGH set input for latch 2. |
| 7 | 2R | input | Active HIGH reset input for latch 2. |
| 8 | VSS | power_in | Ground supply voltage (VSS, usually ground). |
| 9 | 2Q | tri_state | 3-state buffered latch output for latch 2, high impedance when OE is LOW. |
| 10 | 3Q | tri_state | 3-state buffered latch output for latch 3, high impedance when OE is LOW. |
| 11 | 3R | input | Active HIGH reset input for latch 3. |
| 12 | 3S | input | Active HIGH set input for latch 3. |
| 13 | NC | unconnected | Not connected. |
| 14 | 4S | input | Active HIGH set input for latch 4. |
| 15 | 4R | input | Active HIGH reset input for latch 4. |
| 16 | VDD | power_in | Supply voltage, recommended range 3 V to 15 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XBLW |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4043BE - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4043be-etched.step/cd4043be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4043be.step/cd4043be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XBLW datasheet (13 pp, sha256
aa3548f89c1ab184, retrieved 2026-10-14, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4043BE
**XBLW** · Latches · DIP-16
CD4043BE from XBLW, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 4Q | tri_state | 3-state buffered latch output for latch 4, high impedance when OE is LOW. |
| 2 | 1Q | tri_state | 3-state buffered latch output for latch 1, high impedance when OE is LOW. |
| 3 | 1R | input | Active HIGH reset input for latch 1. |
| 4 | 1S | input | Active HIGH set input for latch 1. |
| 5 | OE | input | Common output enable input; outputs are high impedance when LOW and follow the latches when HIGH. |
| 6 | 2S | input | Active HIGH set input for latch 2. |
| 7 | 2R | input | Active HIGH reset input for latch 2. |
| 8 | VSS | power_in | Ground supply voltage (VSS, usually ground). |
| 9 | 2Q | tri_state | 3-state buffered latch output for latch 2, high impedance when OE is LOW. |
| 10 | 3Q | tri_state | 3-state buffered latch output for latch 3, high impedance when OE is LOW. |
| 11 | 3R | input | Active HIGH reset input for latch 3. |
| 12 | 3S | input | Active HIGH set input for latch 3. |
| 13 | NC | unconnected | Not connected. |
| 14 | 4S | input | Active HIGH set input for latch 4. |
| 15 | 4R | input | Active HIGH reset input for latch 4. |
| 16 | VDD | power_in | Supply voltage, recommended range 3 V to 15 V referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XBLW |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `CD4043BE`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `cd4043be-etched.step` / `cd4043be-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4043be.step` / `cd4043be.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [XBLW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590906012431818752) (13 pp, sha256 `aa3548f89c1ab184`, retrieved 2026-10-14, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4043be-datasheet.pdf)