Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	13d ago
viewers	cd4042bpw: viewers · Ray	13d ago
cd4042bpw-etched.glb	Publish 0.1.0 · Ray	13d ago
cd4042bpw-etched.step	cd4042bpw: factory component page (tier=mfr) · Ray	13d ago
cd4042bpw-hero.glb	cd4042bpw: hero GLB from the etched model (keeps the MPN mark) · Ray	13d ago
cd4042bpw-hero.overlay.json	Publish 0.1.0 · Ray	13d ago
cd4042bpw.glb	Publish 0.1.0 · Ray	13d ago
cd4042bpw.kicad_mod	Publish 0.1.0 · Ray	13d ago
cd4042bpw.kicad_sym	Publish 0.1.0 · Ray	13d ago
cd4042bpw.lbr	Publish 0.1.0 · Ray	13d ago
cd4042bpw.step	Publish 0.1.0 · Ray	13d ago
package.json	Publish 0.1.0 · Ray	13d ago
page.json	Set visibility: public · Ray	13d ago
README.md	Publish 0.1.0 · Ray	13d ago

CD4042BPW

Texas Instruments · Latches · TSSOP-16

CD4042BPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q4	output	Buffered true output of latch 4, which follows D4 while the clock/polarity condition is met and holds otherwise.
2	Q1	output	Buffered true output of latch 1, which follows D1 while the clock/polarity condition is met and holds otherwise.
3	Q̄1	output	Buffered complementary output of latch 1, the inverse of Q1.
4	D1	input	Data input of latch 1, protected by a CMOS input network with a maximum input current of ±0.1 µA at 18 V and 25°C.
5	CLOCK	input	Common clock input for all four latches; with POLARITY = 0 data is transferred while CLOCK is 0 and latched on the positive transition.
6	POLARITY	input	Clock polarity control input; with POLARITY = 1 data is transferred while CLOCK is 1 and latched on the negative transition.
7	D2	input	Data input of latch 2, protected by a CMOS input network with a maximum input current of ±0.1 µA at 18 V and 25°C.
8	VSS	power_in	Ground / negative supply terminal, the reference for the VDD rating of -0.5 V to +20 V.
9	Q̄2	output	Buffered complementary output of latch 2, the inverse of Q2.
10	Q2	output	Buffered true output of latch 2, which follows D2 while the clock/polarity condition is met and holds otherwise.
11	Q3	output	Buffered true output of latch 3, which follows D3 while the clock/polarity condition is met and holds otherwise.
12	Q̄3	output	Buffered complementary output of latch 3, the inverse of Q3.
13	D3	input	Data input of latch 3, protected by a CMOS input network with a maximum input current of ±0.1 µA at 18 V and 25°C.
14	D4	input	Data input of latch 4, protected by a CMOS input network with a maximum input current of ±0.1 µA at 18 V and 25°C.
15	Q̄4	output	Buffered complementary output of latch 4, the inverse of Q4.
16	VDD	power_in	Positive supply terminal, recommended 3 V to 18 V and absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Logic ICs
Pins	16

CAD (KiCad official)

Symbol: CD4042BPW
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: cd4042bpw-etched.step / cd4042bpw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4042bpw.step / cd4042bpw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (34 pp, sha256 ef4e092831d2b059, retrieved 2026-10-18, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF