component
CD4042BM
Public Made by Adomby adom
lingxingic Latches, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD4042BM++**lingxingic** · Latches · SOP-16++CD4042BM from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q4 | output | Data output from latch 4. |+| 2 | Q1 | output | Data output from latch 1. |+| 3 | Q̄1 | output | Inverted data output from latch 1. |+| 4 | D1 | input | Data input to latch 1; must be connected to VDD, VSS, or another input if unused. |+| 5 | CLOCK | input | Clock input for all four latches. |+| 6 | POLARITY | input | Clock enable and polarity input; controls latching logic relative to CLOCK. |+| 7 | D2 | input | Data input to latch 2; must be connected to VDD, VSS, or another input if unused. |+| 8 | VSS | power_in | Ground (0V), voltage reference. |+| 9 | Q̄2 | output | Inverted data output from latch 2. |+| 10 | Q2 | output | Data output from latch 2. |+| 11 | Q3 | output | Data output from latch 3. |+| 12 | Q̄3 | output | Inverted data output from latch 3. |+| 13 | D3 | input | Data input to latch 3; must be connected to VDD, VSS, or another input if unused. |+| 14 | D4 | input | Data input to latch 4; must be connected to VDD, VSS, or another input if unused. |+| 15 | Q̄4 | output | Inverted data output from latch 4. |+| 16 | VDD | power_in | Supply voltage, 3V to 15V referenced to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | lingxingic |+| Package | SOP-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4042BM`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)+- 3D model files: `cd4042bm-etched.step` / `cd4042bm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4042bm.step` / `cd4042bm.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603345045894950912) (15 pp, sha256 `e0b95244be641b42`, retrieved 2026-09-17, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4042bm-datasheet.pdf)
page.jsonadded+188@@ -0,0 +1,188 @@+{+ "slug": "cd4042bm",+ "version": "0.1.0",+ "type": "component",+ "description": "lingxingic Latches, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4042bm",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4042bm.kicad_sym",+ "cd4042bm.kicad_mod",+ "cd4042bm.glb",+ "cd4042bm.step",+ "cd4042bm.lbr",+ "docs/hero.png",+ "docs/cd4042bm-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4042BM",+ "manufacturer": "lingxingic",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603345045894950912",+ "parts": {+ "symbol": "cd4042bm.kicad_sym",+ "footprint": "cd4042bm.kicad_mod",+ "model_3d": "cd4042bm-etched.glb",+ "model_3d_plain": "cd4042bm.glb",+ "model_3d_step": "cd4042bm-etched.step",+ "model_3d_step_plain": "cd4042bm.step",+ "lbr": "cd4042bm.lbr"+ },+ "distributor_links": {+ "lcsc": "C22390249"+ },+ "pins": [+ {+ "number": "1",+ "name": "Q4",+ "type": "output",+ "description": "Data output from latch 4."+ },+ {+ "number": "2",+ "name": "Q1",+ "type": "output",+ "description": "Data output from latch 1."+ },+ {+ "number": "3",+ "name": "Q̄1",+ "type": "output",+ "description": "Inverted data output from latch 1."+ },+ {+ "number": "4",+ "name": "D1",+ "type": "input",+ "description": "Data input to latch 1; must be connected to VDD, VSS, or another input if unused."+ },+ {+ "number": "5",+ "name": "CLOCK",+ "type": "input",+ "description": "Clock input for all four latches."+ },+ {+ "number": "6",+ "name": "POLARITY",+ "type": "input",+ "description": "Clock enable and polarity input; controls latching logic relative to CLOCK."+ },+ {+ "number": "7",+ "name": "D2",+ "type": "input",+ "description": "Data input to latch 2; must be connected to VDD, VSS, or another input if unused."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground (0V), voltage reference."+ },+ {+ "number": "9",+ "name": "Q̄2",+ "type": "output",+ "description": "Inverted data output from latch 2."+ },+ {+ "number": "10",+ "name": "Q2",+ "type": "output",+ "description": "Data output from latch 2."+ },+ {+ "number": "11",+ "name": "Q3",+ "type": "output",+ "description": "Data output from latch 3."+ },+ {+ "number": "12",+ "name": "Q̄3",+ "type": "output",+ "description": "Inverted data output from latch 3."+ },+ {+ "number": "13",+ "name": "D3",+ "type": "input",+ "description": "Data input to latch 3; must be connected to VDD, VSS, or another input if unused."+ },+ {+ "number": "14",+ "name": "D4",+ "type": "input",+ "description": "Data input to latch 4; must be connected to VDD, VSS, or another input if unused."+ },+ {+ "number": "15",+ "name": "Q̄4",+ "type": "output",+ "description": "Inverted data output from latch 4."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage, 3V to 15V referenced to VSS."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 15,+ "cost_usd": 0.178,+ "at": "2026-09-17T21:16:39"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603345045894950912",+ "pages": 15,+ "sha256": "e0b95244be641b42",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}