component

CD4042BE

Public Made by Adom

by adom

lingxingic Latches, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4042befactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cd4042be / README.md
History Download
Ray Publish 0.1.0 8f0b720 5d ago

CD4042BE

lingxingic · Latches · DIP-16

CD4042BE from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q4 output Data output of latch 4.
2 Q1 output Data output of latch 1.
3 ~Q1 output Complementary data output of latch 1.
4 D1 input Data input of latch 1; unused inputs must be tied to VDD, VSS or another input.
5 CLOCK input Clock input; with POLARITY low, Q follows D when CLOCK is 0 and latches when CLOCK is 1.
6 POLARITY input Clock enable (polarity) input that selects whether the latch is transparent on low or high CLOCK level.
7 D2 input Data input of latch 2.
8 VSS power_in Ground (0V) reference.
9 ~Q2 output Complementary data output of latch 2.
10 Q2 output Data output of latch 2.
11 Q3 output Data output of latch 3.
12 ~Q3 output Complementary data output of latch 3.
13 D3 input Data input of latch 3.
14 D4 input Data input of latch 4.
15 ~Q4 output Complementary data output of latch 4.
16 VDD power_in Supply voltage, recommended 3V to 15V referenced to VSS.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V Tamb=25℃, referenced to Vss 6
Input voltage VI -0.5 V all inputs; max VDD+0.5 6
DC input current IIK -10 10 mA any one input 6
Storage temperature Tstg -65 150 ℃ 6
Soldering temperature TL 245 ℃ 10s, DIP 6
Supply voltage VDD 3 15 V 6
Ambient temperature Tamb -40 125 ℃ in free air 6
HIGH-level input voltage VIH 3.5 V VDD=5V, Tamb=-40℃ to +125℃ 7
HIGH-level input voltage VIH 7 V VDD=10V, Tamb=-40℃ to +125℃ 7
HIGH-level input voltage VIH 11 V VDD=15V, Tamb=-40℃ to +125℃ 7
LOW-level input voltage VIL 1.5 V VDD=5V, Tamb=-40℃ to +125℃ 7
LOW-level input voltage VIL 3 V VDD=10V, Tamb=-40℃ to +125℃ 7
LOW-level input voltage VIL 4 V VDD=15V, Tamb=-40℃ to +125℃ 7
HIGH-level output voltage VOH 4.95 V VDD=5V, /IO/<1uA 7
HIGH-level output voltage VOH 9.95 V VDD=10V, /IO/<1uA 7
HIGH-level output voltage VOH 14.95 V VDD=15V, /IO/<1uA 7
LOW-level output voltage VOL 0.05 V VDD=5V, /IO/<1uA 7
HIGH-level output current IOH -0.3 mA VDD=5V, VO=4.6V 8
HIGH-level output current IOH -1.15 mA VDD=5V, VO=2.5V 8
HIGH-level output current IOH -0.45 mA VDD=10V, VO=9.5V 8
HIGH-level output current IOH -1.4 mA VDD=15V, VO=13.5V 8
LOW-level output current IOL 0.29 mA VDD=5V, VO=0.4V 8
LOW-level output current IOL 0.38 mA VDD=10V, VO=0.5V 8
LOW-level output current IOL 1.2 mA VDD=15V, VO=1.5V 8
Input leakage current II -1 1 uA VDD=15V, VI=15V or VSS 8
Supply current IDD 30 uA VDD=5V, VI=5V or VSS; IO=0A 8
Supply current IDD 60 uA VDD=10V, VI=10V or VSS; IO=0A 8
Supply current IDD 120 uA VDD=15V, VI=15V or VSS; IO=0A 8
Data in to Q propagation delay time tPHL, tPLH 264 ns VDD=5V, CL=50pF, RL=200kΩ, see Figure 3 9
Data in to Q propagation delay time tPHL, tPLH 132 ns VDD=10V, CL=50pF, RL=200kΩ, see Figure 3 9
Data in to Q propagation delay time tPHL, tPLH 96 ns VDD=15V, CL=50pF, RL=200kΩ, see Figure 3 9
Data in to Q-bar propagation delay time tPHL, tPLH 360 ns VDD=5V, CL=50pF, RL=200kΩ, see Figure 3 9
Data in to Q-bar propagation delay time tPHL, tPLH 180 ns VDD=10V, CL=50pF, RL=200kΩ, see Figure 3 9
Data in to Q-bar propagation delay time tPHL, tPLH 120 ns VDD=15V, CL=50pF, RL=200kΩ, see Figure 3 9
Clock to Q propagation delay time tPHL, tPLH 540 ns VDD=5V, CL=50pF, RL=200kΩ, see Figure 3 9
Clock to Q propagation delay time tPHL, tPLH 240 ns VDD=10V, CL=50pF, RL=200kΩ, see Figure 3 9
Clock to Q propagation delay time tPHL, tPLH 192 ns VDD=15V, CL=50pF, RL=200kΩ, see Figure 3 9
Clock to Q-bar propagation delay time tPHL, tPLH 600 ns VDD=5V, CL=50pF, RL=200kΩ, see Figure 3 9
Clock to Q-bar propagation delay time tPHL, tPLH 276 ns VDD=10V, CL=50pF, RL=200kΩ, see Figure 3 9
Clock to Q-bar propagation delay time tPHL, tPLH 216 ns VDD=15V, CL=50pF, RL=200kΩ, see Figure 3 9
Transition time tTHL, tTLH 240 ns VDD=5V, CL=50pF, RL=200kΩ, see Figure 3 9
Transition time tTHL, tTLH 120 ns VDD=10V, CL=50pF, RL=200kΩ, see Figure 3 9
Transition time tTHL, tTLH 96 ns VDD=15V, CL=50pF, RL=200kΩ, see Figure 3 9
Minimum clock width tw 240 ns VDD=5V, CL=50pF, RL=200kΩ, see Figure 4 9
Minimum clock width tw 120 ns VDD=10V, CL=50pF, RL=200kΩ, see Figure 4 9
Minimum clock width tw 72 ns VDD=15V, CL=50pF, RL=200kΩ, see Figure 4 9
Minimum hold time th 144 ns VDD=5V, CL=50pF, RL=200kΩ, see Figure 4 9
Minimum hold time th 72 ns VDD=10V, CL=50pF, RL=200kΩ, see Figure 4 9
Minimum hold time th 60 ns VDD=15V, CL=50pF, RL=200kΩ, see Figure 4 9
Minimum setup time tsu 60 ns VDD=5V, CL=50pF, RL=200kΩ, see Figure 4 9
Minimum setup time tsu 36 ns VDD=10V, CL=50pF, RL=200kΩ, see Figure 4 9
Minimum setup time tsu 30 ns VDD=15V, CL=50pF, RL=200kΩ, see Figure 4 9

CAD (KiCad official)

  • Symbol: CD4042BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4042be-etched.step / cd4042be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4042be.step / cd4042be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (15 pp, sha256 682336422f705e2f, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF