component
CD4040NS16ARDQ
Public Made by Adomby adom
GR Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 5d ago |
| viewers | 5d ago |
| cd4040ns16ardq-etched.glb | 5d ago |
| cd4040ns16ardq-etched.step | 5d ago |
| cd4040ns16ardq-hero.glb | 5d ago |
| cd4040ns16ardq-hero.overlay.json | 5d ago |
| cd4040ns16ardq.glb | 5d ago |
| cd4040ns16ardq.kicad_mod | 5d ago |
| cd4040ns16ardq.kicad_sym | 5d ago |
| cd4040ns16ardq.lbr | 5d ago |
| cd4040ns16ardq.step | 5d ago |
| package.json | 5d ago |
| page.json | 5d ago |
| README.md | 5d ago |
CD4040NS16ARDQ
GR · Counters, Dividers · SOP-16
CD4040NS16ARDQ from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Parallel binary counter output for stage 12; all outputs are buffered. |
| 2 | Q6 | output | Parallel binary counter output for stage 6; all outputs are buffered. |
| 3 | Q5 | output | Parallel binary counter output for stage 5; all outputs are buffered. |
| 4 | Q7 | output | Parallel binary counter output for stage 7; all outputs are buffered. |
| 5 | Q4 | output | Parallel binary counter output for stage 4; all outputs are buffered. |
| 6 | Q3 | output | Parallel binary counter output for stage 3; all outputs are buffered. |
| 7 | Q2 | output | Parallel binary counter output for stage 2; all outputs are buffered. |
| 8 | VSS | power_in | Ground reference for all voltages; supply and input voltages are referenced to VSS. |
| 9 | Q1 | output | Parallel binary counter output for stage 1; all outputs are buffered. |
| 10 | θ | input | Clock input; the counter advances one count on the HIGH-to-LOW (negative) transition, and Schmitt trigger action permits unlimited rise and fall times. |
| 11 | R | input | Active-HIGH reset input; a high level resets the counter to its all-zeros state. |
| 12 | Q9 | output | Parallel binary counter output for stage 9; all outputs are buffered. |
| 13 | Q8 | output | Parallel binary counter output for stage 8; all outputs are buffered. |
| 14 | Q10 | output | Parallel binary counter output for stage 10; all outputs are buffered. |
| 15 | Q11 | output | Parallel binary counter output for stage 11; all outputs are buffered. |
| 16 | VDD | power_in | Positive supply voltage; the absolute maximum DC supply voltage referenced to VSS is 20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GR |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage Range | VDD | -0.5 | 20 | V | Voltage referenced to VSS terminals | 3 | |
| Input Voltage Range, All Inputs | VI | -0.5 | V | 3 | |||
| Power Dissipation | PD | 500 | mW | 3 | |||
| Junction Temperature | TJ | 125 | ℃ | 3 | |||
| Operating Temperature | TOP | -40 | 85 | ℃ | 3 | ||
| Supply Current | IDD | 0 | 1 | uA | VO=--, VIN=0, VDD=5V, Ta=25℃ | 3 | |
| Low Level Output Current | IOL | 0.5 | 1.5 | mA | VO=0.4V, VIN=0, VDD=5V, Ta=25℃ | 3 | |
| Low Level Output Current | IOL | 2 | 4 | mA | VO=0.5V, VIN=0, VDD=10V, Ta=25℃ | 3 | |
| Low Level Output Current | IOL | 7 | 15 | mA | VO=1.5V, VIN=0, VDD=15V, Ta=25℃ | 3 | |
| High Level Output Current | IOH | -0.5 | -1 | mA | VO=4.6V, VIN=0, VDD=5V, Ta=25℃ | 3 | |
| High Level Output Current | IOH | -2 | -4 | mA | VO=2.5V, VIN=0, VDD=5V, Ta=25℃ | 3 | |
| High Level Output Current | IOH | -1.3 | -2.2 | mA | VO=9.5V, VIN=0, VDD=10V, Ta=25℃ | 3 | |
| High Level Output Current | IOH | -4 | -8 | mA | VO=13.5V, VIN=0, VDD=15V, Ta=25℃ | 3 | |
| Low Level Output Voltage | VOL | 0 | 0.05 | V | VIN=0, VDD=5V, Ta=25℃ | 3 | |
| High Level Output Voltage | VOH | 4.95 | 5 | V | VIN=0, VDD=5V, Ta=25℃ | 3 | |
| High Level Output Voltage | VOH | 9.95 | 10 | V | VIN=0, VDD=10V, Ta=25℃ | 3 | |
| High Level Output Voltage | VOH | 14.95 | 15 | V | VIN=0, VDD=15V, Ta=25℃ | 3 | |
| Low Level Input Voltage | VIL | 1.5 | V | VO=0.5V, 4.5V, VDD=5V, Ta=25℃ | 3 | ||
| Low Level Input Voltage | VIL | 3 | V | VO=1V, 9V, VDD=10V, Ta=25℃ | 3 | ||
| Low Level Input Voltage | VIL | 4 | V | VO=1.5V, 13.5V, VDD=15V, Ta=25℃ | 3 | ||
| High Level Input Voltage | VIH | 3.5 | V | VO=0.5V, 4.5V, VDD=5V, Ta=25℃ | 3 | ||
| High Level Input Voltage | VIH | 7 | V | VO=1V, 9V, VDD=10V, Ta=25℃ | 3 | ||
| High Level Input Voltage | VIH | 11 | V | VO=1.5V, 13.5V, VDD=15V, Ta=25℃ | 3 | ||
| Input Leakage Current | IIN | -1 | 0 | 1 | uA | VO=--, VIN=0, VDD=18V, Ta=25℃ | 3 |
CAD (KiCad official)
- Symbol:
CD4040NS16ARDQ - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4040ns16ardq-etched.step/cd4040ns16ardq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4040ns16ardq.step/cd4040ns16ardq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GR datasheet (7 pp, sha256
0d9e7f289b3a69f3, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).