component
CD4040BE
Public Made by Adomby adom
Texas Instruments Counters, Dividers, DIP-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
main
CD4040BE
Texas Instruments · Counters, Dividers · DIP-16
CD4040BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Buffered output of the 12th counter stage (most significant bit). |
| 2 | Q6 | output | Buffered output of the 6th counter stage. |
| 3 | Q5 | output | Buffered output of the 5th counter stage. |
| 4 | Q7 | output | Buffered output of the 7th counter stage. |
| 5 | Q4 | output | Buffered output of the 4th counter stage. |
| 6 | Q3 | output | Buffered output of the 3rd counter stage. |
| 7 | Q2 | output | Buffered output of the 2nd counter stage. |
| 8 | VSS | power_in | Ground (negative supply) terminal; all voltages are referenced to VSS. |
| 9 | Q1 | output | Buffered output of the 1st counter stage (least significant bit). |
| 10 | φ | input | Input-pulse (clock) line with Schmitt trigger action allowing unlimited rise and fall times; the counter advances one count on the negative transition of each pulse. |
| 11 | RESET | input | Common reset input; a high level resets the counter to its all-zeros state. |
| 12 | Q9 | output | Buffered output of the 9th counter stage. |
| 13 | Q8 | output | Buffered output of the 8th counter stage. |
| 14 | Q10 | output | Buffered output of the 10th counter stage. |
| 15 | Q11 | output | Buffered output of the 11th counter stage. |
| 16 | VDD | power_in | Positive supply terminal; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4040BE - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4040be-etched.step/cd4040be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4040be.step/cd4040be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
21262dd0397becc8, retrieved 2026-10-21, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4040BE
**Texas Instruments** · Counters, Dividers · DIP-16
CD4040BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Buffered output of the 12th counter stage (most significant bit). |
| 2 | Q6 | output | Buffered output of the 6th counter stage. |
| 3 | Q5 | output | Buffered output of the 5th counter stage. |
| 4 | Q7 | output | Buffered output of the 7th counter stage. |
| 5 | Q4 | output | Buffered output of the 4th counter stage. |
| 6 | Q3 | output | Buffered output of the 3rd counter stage. |
| 7 | Q2 | output | Buffered output of the 2nd counter stage. |
| 8 | VSS | power_in | Ground (negative supply) terminal; all voltages are referenced to VSS. |
| 9 | Q1 | output | Buffered output of the 1st counter stage (least significant bit). |
| 10 | φ | input | Input-pulse (clock) line with Schmitt trigger action allowing unlimited rise and fall times; the counter advances one count on the negative transition of each pulse. |
| 11 | RESET | input | Common reset input; a high level resets the counter to its all-zeros state. |
| 12 | Q9 | output | Buffered output of the 9th counter stage. |
| 13 | Q8 | output | Buffered output of the 8th counter stage. |
| 14 | Q10 | output | Buffered output of the 10th counter stage. |
| 15 | Q11 | output | Buffered output of the 11th counter stage. |
| 16 | VDD | power_in | Positive supply terminal; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `CD4040BE`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `cd4040be-etched.step` / `cd4040be-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4040be.step` / `cd4040be.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4024b) (30 pp, sha256 `21262dd0397becc8`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4040be-datasheet.pdf)