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CD4035BM96
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD4035BM96
Texas Instruments · Shift Registers · SOIC-16
CD4035BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1/Q̄1 | output | Stage 1 buffered output, true or complement depending on TRUE/COMPLEMENT control. |
| 2 | T/C | input | TRUE/COMPLEMENT control: high gives true register contents at outputs, low gives complements; acts asynchronously with respect to clock. |
| 3 | K̄ | input | Inverted K serial input to first stage JK logic; with J and K tied together the first stage acts as a D flip-flop. |
| 4 | J | input | J serial input to first stage JK logic. |
| 5 | RESET | input | Asynchronous common reset for the register. |
| 6 | CLK | input | Clock input; data is transferred on positive clock transitions in parallel or serial mode. |
| 7 | P/S | input | PARALLEL/SERIAL control: high permits synchronous parallel entry, low selects serial mode. |
| 8 | VSS | power_in | Ground (VSS); supply voltage is referenced to this terminal. |
| 9 | PI-1 | input | Parallel input to stage 1. |
| 10 | PI-2 | input | Parallel input to stage 2. |
| 11 | PI-3 | input | Parallel input to stage 3. |
| 12 | PI-4 | input | Parallel input to stage 4. |
| 13 | Q4/Q̄4 | output | Stage 4 buffered output, true or complement depending on TRUE/COMPLEMENT control. |
| 14 | Q3/Q̄3 | output | Stage 3 buffered output, true or complement depending on TRUE/COMPLEMENT control. |
| 15 | Q2/Q̄2 | output | Stage 2 buffered output, true or complement depending on TRUE/COMPLEMENT control. |
| 16 | VDD | power_in | Positive supply; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4035BM96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cd4035bm96-etched.step/cd4035bm96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4035bm96.step/cd4035bm96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (18 pp, sha256
cbad6c2b0483fd56, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4035BM96
**Texas Instruments** · Shift Registers · SOIC-16
CD4035BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1/Q̄1 | output | Stage 1 buffered output, true or complement depending on TRUE/COMPLEMENT control. |
| 2 | T/C | input | TRUE/COMPLEMENT control: high gives true register contents at outputs, low gives complements; acts asynchronously with respect to clock. |
| 3 | K̄ | input | Inverted K serial input to first stage JK logic; with J and K tied together the first stage acts as a D flip-flop. |
| 4 | J | input | J serial input to first stage JK logic. |
| 5 | RESET | input | Asynchronous common reset for the register. |
| 6 | CLK | input | Clock input; data is transferred on positive clock transitions in parallel or serial mode. |
| 7 | P/S | input | PARALLEL/SERIAL control: high permits synchronous parallel entry, low selects serial mode. |
| 8 | VSS | power_in | Ground (VSS); supply voltage is referenced to this terminal. |
| 9 | PI-1 | input | Parallel input to stage 1. |
| 10 | PI-2 | input | Parallel input to stage 2. |
| 11 | PI-3 | input | Parallel input to stage 3. |
| 12 | PI-4 | input | Parallel input to stage 4. |
| 13 | Q4/Q̄4 | output | Stage 4 buffered output, true or complement depending on TRUE/COMPLEMENT control. |
| 14 | Q3/Q̄3 | output | Stage 3 buffered output, true or complement depending on TRUE/COMPLEMENT control. |
| 15 | Q2/Q̄2 | output | Stage 2 buffered output, true or complement depending on TRUE/COMPLEMENT control. |
| 16 | VDD | power_in | Positive supply; recommended range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `CD4035BM96`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `cd4035bm96-etched.step` / `cd4035bm96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4035bm96.step` / `cd4035bm96.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4035bm96.pdf) (18 pp, sha256 `cbad6c2b0483fd56`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4035bm96-datasheet.pdf)