component
CD4030BE
Public Made by Adomby adom
Texas Instruments Logic Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD4030BE
Texas Instruments · Logic Gates · PDIP-14
CD4030BE from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of gate 1 (J = A XOR B); inputs limited to -0.5 V to VDD+0.5 V. |
| 2 | B | input | Input B of gate 1 (J = A XOR B); inputs limited to -0.5 V to VDD+0.5 V. |
| 3 | J | output | Output of gate 1, J = A XOR B. |
| 4 | K | output | Output of gate 2, K = C XOR D. |
| 5 | C | input | Input C of gate 2 (K = C XOR D); inputs limited to -0.5 V to VDD+0.5 V. |
| 6 | D | input | Input D of gate 2 (K = C XOR D); inputs limited to -0.5 V to VDD+0.5 V. |
| 7 | VSS | power_in | Ground (negative supply) reference terminal. |
| 8 | E | input | Input E of gate 3 (L = E XOR F); inputs limited to -0.5 V to VDD+0.5 V. |
| 9 | F | input | Input F of gate 3 (L = E XOR F); inputs limited to -0.5 V to VDD+0.5 V. |
| 10 | L | output | Output of gate 3, L = E XOR F. |
| 11 | M | output | Output of gate 4, M = G XOR H. |
| 12 | G | input | Input G of gate 4 (M = G XOR H); inputs limited to -0.5 V to VDD+0.5 V. |
| 13 | H | input | Input H of gate 4 (M = G XOR H); inputs limited to -0.5 V to VDD+0.5 V. |
| 14 | VDD | power_in | Positive supply, recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V relative to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature range | -55 | 125 | °C | Op temp column, CD4030BE PDIP (N) 14-pin, package addendum | 4 |
CAD (KiCad official)
- Symbol:
CD4030BE - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4030be-etched.step/cd4030be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4030be.step/cd4030be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
04f95a759b6780e5, retrieved 2026-10-13, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4030BE
**Texas Instruments** · Logic Gates · PDIP-14
CD4030BE from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of gate 1 (J = A XOR B); inputs limited to -0.5 V to VDD+0.5 V. |
| 2 | B | input | Input B of gate 1 (J = A XOR B); inputs limited to -0.5 V to VDD+0.5 V. |
| 3 | J | output | Output of gate 1, J = A XOR B. |
| 4 | K | output | Output of gate 2, K = C XOR D. |
| 5 | C | input | Input C of gate 2 (K = C XOR D); inputs limited to -0.5 V to VDD+0.5 V. |
| 6 | D | input | Input D of gate 2 (K = C XOR D); inputs limited to -0.5 V to VDD+0.5 V. |
| 7 | VSS | power_in | Ground (negative supply) reference terminal. |
| 8 | E | input | Input E of gate 3 (L = E XOR F); inputs limited to -0.5 V to VDD+0.5 V. |
| 9 | F | input | Input F of gate 3 (L = E XOR F); inputs limited to -0.5 V to VDD+0.5 V. |
| 10 | L | output | Output of gate 3, L = E XOR F. |
| 11 | M | output | Output of gate 4, M = G XOR H. |
| 12 | G | input | Input G of gate 4 (M = G XOR H); inputs limited to -0.5 V to VDD+0.5 V. |
| 13 | H | input | Input H of gate 4 (M = G XOR H); inputs limited to -0.5 V to VDD+0.5 V. |
| 14 | VDD | power_in | Positive supply, recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V relative to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating temperature range | | -55 | | 125 | °C | Op temp column, CD4030BE PDIP (N) 14-pin, package addendum | 4 |
## CAD (KiCad official)
- Symbol: `CD4030BE`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4030be-etched.step` / `cd4030be-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4030be.step` / `cd4030be.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4030b-mil) (20 pp, sha256 `04f95a759b6780e5`, retrieved 2026-10-13, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4030be-datasheet.pdf)