component
CD4029BPWR
Public Made by Adomby adom
Texas Instruments Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4029BPWR
Texas Instruments · Counters, Dividers · TSSOP-16
CD4029BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PRESET ENABLE | input | High level asynchronously loads the JAM inputs into the counter; input voltage range -0.5V to VDD+0.5V. |
| 2 | Q4 | output | Buffered counter output Q4 (BCD output in decade mode). |
| 3 | JAM 4 | input | Jam (preset) input 4, loaded into the counter when PRESET ENABLE is high. |
| 4 | JAM 1 | input | Jam (preset) input 1, loaded into the counter when PRESET ENABLE is high. |
| 5 | CARRY IN | input | Active-low carry-in (clock enable) input; must be connected to VSS when not in use. |
| 6 | Q1 | output | Buffered counter output Q1. |
| 7 | CARRY OUT | output | Active-low carry output, normally high and goes low at maximum count in UP mode or minimum count in DOWN mode when CARRY IN is low. |
| 8 | VSS | power_in | Ground/negative supply terminal; all voltage ratings are referenced to VSS. |
| 9 | BINARY/DECADE | input | High selects binary counting, low selects decade counting. |
| 10 | UP/DOWN | input | High counts up, low counts down. |
| 11 | Q2 | output | Buffered counter output Q2. |
| 12 | JAM 2 | input | Jam (preset) input 2, loaded into the counter when PRESET ENABLE is high. |
| 13 | JAM 3 | input | Jam (preset) input 3, loaded into the counter when PRESET ENABLE is high. |
| 14 | Q3 | output | Buffered counter output Q3. |
| 15 | CLOCK | input | Clock input; counter advances on the positive clock transition, with max clock input frequency 2 MHz at 5V, 4 MHz at 10V, 5.5 MHz at 15V. |
| 16 | VDD | power_in | Positive supply; recommended range 3V to 18V, absolute maximum -0.5V to +20V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4029BPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4029bpwr-etched.step/cd4029bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4029bpwr.step/cd4029bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
67cc8d6987a766ba, retrieved 2026-10-01, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).